ROMC - Revision history

E5frog at 08:53, 30 August 2024

2024-08-30T08:53:08Z

E5frog: /* The different states */

2024-08-26T15:40:18Z

‎The different states

E5frog: /* The different states */

2022-09-26T15:51:05Z

‎The different states

E5frog at 14:03, 26 September 2022

2022-09-26T14:03:37Z

E5frog at 14:03, 26 September 2022

2022-09-26T14:03:10Z

E5frog at 14:02, 26 September 2022

2022-09-26T14:02:44Z

E5frog at 13:49, 26 September 2022

2022-09-26T13:49:01Z

E5frog at 13:42, 12 April 2022

2022-04-12T13:42:06Z

E5frog at 09:32, 8 September 2016

2016-09-08T09:32:43Z

E5frog at 09:32, 8 September 2016

2016-09-08T09:32:02Z

@@ Line 1: / Line 1: @@
-To save on capsule pins the different parts in the F8 processor system communicates with the ROMC-bus.<br>
+To save on capsule pins the different devices in the F8 processor system communicates with the ROMC-bus.<br>
-Instead of an address bus each device has its own Program Counter (PC). <br>
+Instead of using an address bus each device has its own Program Counter (PC) as well as a couple of other registers<br>
-A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles). <br>
+A '''S'''hort cycle is 4 clock periods long, a '''L'''ong cycle is 6 clock periods long (sometimes referred to 1.5 cycles). <br>
 == The different states ==

@@ Line 131: / Line 131: @@
 |L
 |The interrupting device with highest priority must move the high order half of the interrupt vector onto<br>
-data bus. All devices must move the contents of the data bus into the high order byte of PC0. The<br>
+the data bus. All devices must move the contents of the data bus into the high order byte of PC0. The<br>
-interrupting device resets its interupt circuitry (so that it is no longer requesting CPU servicing and can <br>
+interrupting device resets its interrupt circuitry (so that it is no longer requesting CPU servicing and can <br>
 respond to another interrupt).
 |-
@@ Line 139: / Line 139: @@
 |14
 |L
-|All devices move the contents of the data bus into the high low order byte of PC0.
+|All devices move the contents of the data bus into the high order byte of PC0.
 |-
 |10101

@@ Line 99: / Line 99: @@
 |L
 |The device whose address space includes the contents of PC0 must place the contents of the word <br>
-adressed by PC0 onto the data bus. The value on the data bus is then moved tot the low order byte<br>
+adressed by PC0 onto the data bus. The value on the data bus is then moved to the low order byte<br>
 of DC0 by all devices
 |-

@@ Line 3: / Line 3: @@
 A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles). <br>
 The different states
 {| class="wikitable" style="text-align: center;"

@@ Line 2: / Line 2: @@
 Instead of an address bus each device has its own Program Counter (PC). <br>
-A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles).
+A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles). <br>
 The different states

@@ Line 103: / Line 103: @@
 |L
 |The interrupting device with highest priority must place the low order byte of the interrupt vector on the<br>
-data bus. All devices must copy the contents of PC0 into PC1. All devices must moce the contents of <br>
+data bus. All devices must copy the contents of PC0 into PC1. All devices must move the contents of <br>
 the data bus into the low order byte of PC0.
 |-

@@ Line 14: / Line 14: @@
 |00
 |S,L
-|Instruction Fetch. The device whose address space includes the contents of the PCO register must <br>
+|Instruction Fetch. The device whose address space includes the contents of the PC0 register must <br>
 place on the data bus the op code addressed by PC0; then all devices increment the contents of PC0.
 |-
@@ Line 20: / Line 20: @@
 |01
 |L
-|The device whose address space includes the contents of the PCO register must place on the data bus <br>
+|The device whose address space includes the contents of the PC0 register must place on the data bus <br>
 the contents of the memory location addressed by PC0; then all devices add the 8-bit value on the data<br>
 bus, as as signed binary number, to PC0.
@@ Line 190: / Line 190: @@
 |1E
 |L
-|The device whose address space includes the contents of PCO must place the low order byte of PCO<br>
+|The device whose address space includes the contents of PC0 must place the low order byte of PC0<br>
 onto the data bus.
 |-
@@ Line 196: / Line 196: @@
 |1F
 |L
-|The device whose address space includes the contents of PCO must place the high order byte of PCO<br>
+|The device whose address space includes the contents of PC0 must place the high order byte of PC0<br>
 onto the data bus.
 |}

@@ Line 14: / Line 14: @@
 |00
 |S,L
-|Instruction Fetch. The device whose address space includes the contents of the PC0 register must
+|Instruction Fetch. The device whose address space includes the contents of the PCO register must <br>
 place on the data bus the op code addressed by PC0; then all devices increment the contents of PC0.
 |-
@@ Line 20: / Line 20: @@
 |01
 |L
-|The device whose address space includes the contents of the PC0 register must place on the data bus
+|The device whose address space includes the contents of the PCO register must place on the data bus <br>
-the contents of the memory location addressed by PC0; then all devices add the 8-bit value on the data
+the contents of the memory location addressed by PC0; then all devices add the 8-bit value on the data<br>
 bus, as as signed binary number, to PC0.
 |-
@@ Line 27: / Line 27: @@
 |02
 |L
-|The device whose DC0 addresses a memory word within the address space of that device must
+|The device whose DC0 addresses a memory word within the address space of that device must <br>
-place on the data bus the contents of the memory location addressed by DC0; then all devices
+place on the data bus the contents of the memory location addressed by DC0; then all devices <br>
 increment DC0.
 |-
@@ Line 34: / Line 34: @@
 |03
 |L,S
-|Similar to 00, except that it is used for Immediate Operand fetches (using PC0) instead of
+|Similar to 00, except that it is used for Immediate Operand fetches (using PC0) instead of <br>
 instruction fetches.
 |-
@@ Line 60: / Line 60: @@
 |08
 |L
-|All devices copy the contents of PC0 into PC1. The CPU outputs zero on the data bus in this ROMC
+|All devices copy the contents of PC0 into PC1. The CPU outputs zero on the data bus in this ROMC<br>
 state. Load the data bus into both halves of PC0, thus clearing the register.
 |-
@@ Line 66: / Line 66: @@
 |09
 |L
-|The device whose address space includes the contents of the DC0 register must place the low order
+|The device whose address space includes the contents of the DC0 register must place the low order<br>
 byte of DC0 onto the data bus.
 |-
@@ Line 77: / Line 77: @@
 |0B
 |L
-|The device whose address space includes the value in PC1 must place the low order byte of PC1 on
+|The device whose address space includes the value in PC1 must place the low order byte of PC1 on<br>
 the data bus.
 |-
@@ Line 83: / Line 83: @@
 |0C
 |L
-|The device whose address space includes the contents of the PC0 register must place the contents of
+|The device whose address space includes the contents of the PC0 register must place the contents of<br>
-the memory word addressed by PC0 onto the data bus; then all devices move the value that has just
+the memory word addressed by PC0 onto the data bus; then all devices move the value that has just <br>
 been placed on the data bus into the low order byte of PC0.
 |-
@@ Line 95: / Line 95: @@
 |0E
 |L
-|The device whose address space includes the contents of PC0 must place the contents of the word
+|The device whose address space includes the contents of PC0 must place the contents of the word <br>
-adressed by PC0 onto the data bus. The value on the data bus is then moved tot the low order byte
+adressed by PC0 onto the data bus. The value on the data bus is then moved tot the low order byte<br>
 of DC0 by all devices
 |-
@@ Line 102: / Line 102: @@
 |0F
 |L
-|The interrupting device with highest priority must place the low order byte of the interrupt vector on the
+|The interrupting device with highest priority must place the low order byte of the interrupt vector on the<br>
-data bus. All devices must copy the contents of PC0 into PC1. All devices must moce the contents of
+data bus. All devices must copy the contents of PC0 into PC1. All devices must moce the contents of <br>
 the data bus into the low order byte of PC0.
 |-
@@ Line 114: / Line 114: @@
 |11
 |L
-|The device whose memory space includes the contents of PC0 must place the contents of the
+|The device whose memory space includes the contents of PC0 must place the contents of the<br>
-addressed memory word onto the data bus. All devices must then move the contents of the data bus
+addressed memory word onto the data bus. All devices must then move the contents of the data bus<br>
 to the upper byte of DC0.
 |-
@@ Line 121: / Line 121: @@
 |12
 |L
-|All devices copy the contents of PC0 into PC1. All devices then move the contents of the data bus into
+|All devices copy the contents of PC0 into PC1. All devices then move the contents of the data bus into<br>
 the low order byte of PC0.
 |-
@@ Line 127: / Line 127: @@
 |13
 |L
-|The interrupting device with highest priority must move the high order half of the interrupt vector onto
+|The interrupting device with highest priority must move the high order half of the interrupt vector onto<br>
-data bus. All devices must move the contents of the data bus into the high order byte of PC0. The
+data bus. All devices must move the contents of the data bus into the high order byte of PC0. The<br>
-interrupting device resets its interupt circuitry (so that it is no longer requesting CPU servicing and can
+interrupting device resets its interupt circuitry (so that it is no longer requesting CPU servicing and can <br>
 respond to another interrupt).
 |-
@@ Line 166: / Line 166: @@
 |1A
 |L
-|During the prior cycle, an I/O port timer or interrupt control register was addressed; the device
+|During the prior cycle, an I/O port timer or interrupt control register was addressed; the device <br>
 containing the addressed port must move the current contents of the data bus  into the addressed port.
 |-
@@ Line 172: / Line 172: @@
 |1B
 |L
-|During the prior cycle, the data bus specified the address of an I/O port. The device containing the
+|During the prior cycle, the data bus specified the address of an I/O port. The device containing the <br>
-addressed I/O port must place the contents of the I/O port on the data bus. (Note that the contents of
+addressed I/O port must place the contents of the I/O port on the data bus. (Note that the contents of <br>
 timer and interrupt control registers cannot be read back onto the data bus.)
 |-
@@ Line 184: / Line 184: @@
 |1D
 |S
-|Devices with DC0 and DC1 registers must switch registers. Devices without a DC1 register perform no
+|Devices with DC0 and DC1 registers must switch registers. Devices without a DC1 register perform no <br>
 operation.
 |-
@@ Line 190: / Line 190: @@
 |1E
 |L
-|The device whose address space includes the contents of PC0 must place the low order byte of PC0
+|The device whose address space includes the contents of PCO must place the low order byte of PCO<br>
 onto the data bus.
 |-
@@ Line 196: / Line 196: @@
 |1F
 |L
-|The device whose address space includes the contents of PC0 must place the high order byte of PC0
+|The device whose address space includes the contents of PCO must place the high order byte of PCO<br>
 onto the data bus.
 |}