Difference between revisions of "Opcode"
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| − | An '''opcode''' is | + | An '''opcode''' is representing an instruction for the [[F8|F8 processor system]] to follow for example the machine code $2B means No Operation (NOP). Programs are made up of opcodes which instruct the F8 System to do something, such as load a register with a value, perform arithmetic on a register, change the program counter (jump), or input or output data through the [[port|ports]]. Opcodes in the F8 System are each one byte wide, though some may be followed by an address (two bytes) or a value for the opcode to use. The mnemonics are constructed so we people can understand it easier than just looking at rows of numbers. NOP is such a mnemonic and can be used in an assembly program listing. |
== The Instruction Set == | == The Instruction Set == | ||
Revision as of 14:49, 22 November 2012
An opcode is representing an instruction for the F8 processor system to follow for example the machine code $2B means No Operation (NOP). Programs are made up of opcodes which instruct the F8 System to do something, such as load a register with a value, perform arithmetic on a register, change the program counter (jump), or input or output data through the ports. Opcodes in the F8 System are each one byte wide, though some may be followed by an address (two bytes) or a value for the opcode to use. The mnemonics are constructed so we people can understand it easier than just looking at rows of numbers. NOP is such a mnemonic and can be used in an assembly program listing.
The Instruction Set
In the information for each opcode, the following notations are used:
| Opcode Notations | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| A | Accumulator | ||||||||
| Ri | Scratchpad register i (r0-r11) | ||||||||
| P0 | Program counter | ||||||||
| P | Program counter Stack | ||||||||
| DC0 | Data counter | ||||||||
| DC1 | Alternate data counter | ||||||||
| W | Status register | ||||||||
| ISAR | Indirect Scratchpad Address Register | ||||||||
| r | Scratchpad addressing as:
| ||||||||
| t | 3-bit constant | ||||||||
| i | 4-bit constant | ||||||||
| n | 8-bit constant | ||||||||
| mn | 16-bit constant | ||||||||
| ( ) | Contents of memory (e.g., (DC)) | ||||||||
| x | Binary value placeholder | ||||||||
| Status Flag Notations | |||||||||
| O | Overflow Flag | ||||||||
| Z | Zero Flag | ||||||||
| C | Carry Flag | ||||||||
| S | Sign Flag | ||||||||
| 0 | Resets status flag | ||||||||
| 1 | Sets status flag | ||||||||
| X | Modifies status flag | ||||||||
| Mnemonic | Length | Cycles | Description | Opcode | Status Flags | ||||
|---|---|---|---|---|---|---|---|---|---|
| Binary | Hex | O | Z | C | S | ||||
| LR A, Ku | 1 | 1 | A = R12 | %00000000 | $00 | - | - | - | - |
| LR A, Kl | 1 | 1 | A = R13 | %00000001 | $01 | - | - | - | - |
| LR A, Qu | 1 | 1 | A = R14 | %00000010 | $02 | - | - | - | - |
| LR A, Ql | 1 | 1 | A = R15 | %00000011 | $03 | - | - | - | - |
| LR Ku, A | 1 | 1 | R12 = A | %00000100 | $04 | - | - | - | - |
| LR Kl, A | 1 | 1 | R13 = A | %00000101 | $05 | - | - | - | - |
| LR Qu, A | 1 | 1 | R14 = A | %00000110 | $06 | - | - | - | - |
| LR Ql, A | 1 | 1 | R15 = A | %00000111 | $07 | - | - | - | - |
| LR K, P | 1 | 4 | R12=PC1(u), R13=PC1(l) | %00001000 | $08 | - | - | - | - |
| LR P, K | 1 | 4 | PC1(u)=R12, PC1(l)=R13 | %00001001 | $09 | - | - | - | - |
| LR A, IS | 1 | 1 | A = ISAR | %00001010 | $0A | - | - | - | - |
| LR IS, A | 1 | 1 | ISAR = A | %00001011 | $0B | - | - | - | - |
| PK | 1 | 2.5 | PC1<-(PC0), PC0(l)<-R13, PC0(u)<-R12 | %00001100 | $0C | - | - | - | - |
| LR P0, Q | 1 | 4 | PC0(u)=R14, PC0(l)=R15 | %00001101 | $0D | - | - | - | - |
| LR Q, DC | 1 | 4 | R14=DC0(u), R15=DC0(l) | %00001110 | $0E | - | - | - | - |
| LR DC, Q | 1 | 4 | DC0(u)=R14, DC0(l)=R15 | %00001111 | $0F | - | - | - | - |
| LR DC, H | 1 | 4 | DC0(u)=R10, DC0(l)=R11 | %00010000 | $10 | - | - | - | - |
| LR H, DC | 1 | 4 | R10=DC0(u), R11=DC0(l) | %00010001 | $11 | - | - | - | - |
| SR 1 | 1 | 1 | Shift A right one bit, fill with %0 | %00010010 | $12 | 0 | X | 0 | 1 |
| SL 1 | 1 | 1 | Shift A left one bit, fill with %0 | %00010011 | $13 | 0 | X | 0 | X |
| SR 4 | 1 | 1 | Shift A right four bits, fill with %0000 | %00010100 | $14 | 0 | X | 0 | 1 |
| SL 4 | 1 | 1 | Shift A left four bits, fill with %0000 | %00010101 | $15 | 0 | X | 0 | X |
| LM | 1 | 2.5 | A = (DC0), DC0 = DC0 + 1 | %00010110 | $16 | - | - | - | - |
| ST | 1 | 2.5 | (DC0) = A, DC0 = DC0 + 1 | %00010111 | $17 | - | - | - | - |
| COM | 1 | 1 | A = [[complement] of A (inverse) | %00011000 | $18 | 0 | X | 0 | X |
| LNK | 1 | 1 | A <- (A)+(C) | %00011001 | $19 | X | X | X | X |
| DI | 1 | 1 | Disable interrupts in status register bit 4 | %00011010 | $1A | - | - | - | - |
| EI | 1 | 1 | Enable interrupts in status register bit 4 | %00011011 | $1B | - | - | - | - |
| POP | 1 | 2 | PC0 <- PC1, A destroyed | %00011100 | $1C | - | - | - | - |
| LR J, W | 1 | 1 | R9 = W | %00011101 | $1D | - | - | - | - |
| LR W, J | 1 | 2 | W = R9 | %00011110 | $1E | - | - | - | - |
| INC | 1 | 1 | A <- (A)+1 | %00011111 | $1F | X | X | X | X |
| LI n | 2 | 2.5 | A = n | %00100000 %xxxxxxxx | $20 $xx | - | - | - | - |
| NI n | 2 | 2.5 | A <- (A) AND n | %00100001 %xxxxxxxx | $21 $xx | 0 | X | 0 | X |
| OI n | 2 | 2.5 | A <- (A) OR n | %00100010 %xxxxxxxx | $22 $xx | 0 | X | 0 | X |
| XI n | 2 | 2.5 | A <- (A) XOR n | %00100011 %xxxxxxxx | $23 $xx | 0 | X | 0 | X |
| AI n | 2 | 2.5 | A = A + n | %00100100 %xxxxxxxx | $24 $xx | X | X | X | X |
| CI n | 2 | 2.5 | n - (A), Only set status | %00100101 %xxxxxxxx | $25 $xx | X | X | X | X |
| IN n | 2 | 4 | Input port n to A | %00100110 %xxxxxxxx | $26 $xx | 0 | X | 0 | X |
| OUT n | 2 | 4 | Output A to port n | %00100111 %xxxxxxxx | $27 $xx | - | - | - | - |
| PI mn | 3 | 6.5 | A<-m, PC1<-(PC0)+1, PC0(l)<-n, PC0(u)<-(A) | %00101000 %xxxxxxxx %xxxxxxxx | $28 $xx $xx | - | - | - | - |
| JMP mn | 3 | 5.5 | PC0 = mn, A is destroyed | %00101001 %xxxxxxxx %xxxxxxxx | $29 $xx $xx | - | - | - | - |
| DCI mn | 3 | 6 | DC0=mn | %00101010 %xxxxxxxx %xxxxxxxx | $2A $xx $xx | - | - | - | - |
| NOP | 1 | 1 | No operation (cycle waster) | %00101011 | $2B | - | - | - | - |
| XDC | 1 | 2 | DC0=DC1, DC1=DC0 | %00101100 | $2C | - | - | - | - |
| DS r | 1 | 1.5 | r <- (r)+$ff | %0011xxxx | $3x | X | X | X | X |
| LR A, r | 1 | 1 | A = r | %0100xxxx | $4x | - | - | - | - |
| LR r, A | 1 | 1 | r = A | %0101xxxx | $5x | - | - | - | - |
| LISU i | 1 | 1 | ISAR(u) = i | %01100xxx | $6x | - | - | - | - |
| LISL i | 1 | 1 | ISAR(l) = i | %01101xxx | $6x | - | - | - | - |
| LIS i | 1 | 1 | A = i | %0111xxxx | $7x | - | - | - | - |
| CLR | 1 | 1 | A = 0 | %01110000 | $70 | - | - | - | - |
| BT t, n | 2 | 3 (no branch) 3.5 (branch) |
AND bitmask t with W, if result = TRUE: P0 = P0 + 1 + n | %10000xxx %xxxxxxxx | $8x | - | - | - | - |
| BP n | 2 | 3 (no branch) 3.5 (branch) |
if POSITIVE: P0 = P0 + 1 + n | %10000001 %xxxxxxxx | $81 $xx | - | - | - | - |
| BC n | 2 | 3 (no branch) 3.5 (branch) |
if CARRY: P0 = P0 + 1 + n | %10000010 %xxxxxxxx | $82 $xx | - | - | - | - |
| BZ n | 2 | 3 (no branch) 3.5 (branch) |
if ZERO: P0 = P0 + 1 + n | %10000100 %xxxxxxxx | $84 $xx | - | - | - | - |
| AM | 1 | 2.5 | A <- (A)+((DC0)), DC0++ | %10001000 | $88 | X | X | X | X |
| AMD | 1 | 2.5 | A <- (A)+((DC0)) decimal adjusted, DC0++ | %10001001 | $89 | X | X | X | X |
| NM | 1 | 2.5 | A <-(A)AND((DC0)),DC0++ | %10001010 | $8A | 0 | X | 0 | X |
| OM | 1 | 2.5 | A <-(A)OR((DC0)),DC0++ | %10001011 | $8B | 0 | X | 0 | X |
| XM | 1 | 2.5 | A <-(A)XOR((DC0)),DC0++ | %10001100 | $8C | 0 | X | 0 | X |
| CM | 1 | 2.5 | ((DC0))-A only set status, DC0++ | %10001101 | $8D | X | X | X | X |
| ADC | 1 | 2.5 | DC0=DC0+A | %10001110 | $8E | - | - | - | - |
| BR7 n | 2 | 2 (no branch) 2.5 (branch) |
if ISAR(l) != 7: P0 = P0 + 1 + n | %10001111 %xxxxxxxx | $8F $xx | - | - | - | - |
| BF i, n | 2 | 3 (no branch) 3.5 (branch) |
AND bitmask i with W, if result = FALSE: PC0=PC0 + 1 + n | %1001xxxx %xxxxxxxx | $9x | - | - | - | - |
| BR n | 2 | 3.5 | P0 = P0 + 1 + n | %10010000 %xxxxxxxx | $90 $xx | - | - | - | - |
| BM n | 2 | 3 (no branch) 3.5 (branch) |
if NEGATIVE: P0 = P0 + 1 + n | %10010001 %xxxxxxxx | $91 $xx | - | - | - | - |
| BNC n | 2 | 3 (no branch) 3.5 (branch) |
if NO CARRY: P0 = P0 + 1 + n | %10010010 %xxxxxxxx | $92 $xx | - | - | - | - |
| BNZ n | 2 | 3 (no branch) 3.5 (branch) |
if NOT ZERO: P0 = P0 + 1 + n | %10010100 %xxxxxxxx | $94 $xx | - | - | - | - |
| BNO n | 2 | 3 (no branch) 3.5 (branch) |
if NO OVERFLOW: P0 = P0 + 1 + n | %10011000 %xxxxxxxx | $98 $xx | - | - | - | - |
| INS i | 1 | 2 (i=0-1) 4 (i=2-15) |
Input port i to A | %1010xxxx | $Ax | 0 | X | 0 | X |
| OUTS i | 1 | 2 (i=0-1) 4 (i=2-15) |
Output A to port i | %1011xxxx | $Bx | - | - | - | - |
| AS r | 1 | 1 | A = A + r | %1100xxxx | $Cx | X | X | X | X |
| ASD r | 1 | 2 | A <-(A)+(r) decimal | %1101xxxx | $Dx | X | X | X | X |
| XS r | 1 | 1 | A <-(A)XOR(r) | %1110xxxx | $Ex | 0 | X | 0 | X |
| NS r | 1 | 1 | A <-(A)AND(r) | %1111xxxx | $Fx | 0 | X | 0 | X |
| IRQ | 5.5 | PC0(l)<-Int address(l), PC0(u)<-Int.Address(u), PC1<-PC0 | - | - | - | - | |||
| RESET | 3.5 | PC0<-0, PC1<-PC0 | - | - | - | - | |||
