Difference between revisions of "Opcode"

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(→‎The Instruction Set)
(→‎The Instruction Set)
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! rowspan="2" | Cycles
 
! rowspan="2" | Cycles
 
! rowspan="2" | Description
 
! rowspan="2" | Description
−
! colspan="2" | OPC0de
+
! colspan="2" | Opcode
 
! colspan="4" class="unsortable" | Status Flags
 
! colspan="4" class="unsortable" | Status Flags
 
|-
 
|-
Line 96: Line 96:
 
| LR Ql, A || 1 || 1 || R15 ← (A) || %00000111 || $07 ||- ||- ||- ||-
 
| LR Ql, A || 1 || 1 || R15 ← (A) || %00000111 || $07 ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR K, P || 1 || 4 || R12←(PC1U), R13←(PC1L) || %00001000 || $08 ||- ||- ||- ||-
+
| LR K, P || 1 || 4 || R12 ← (PC1U), R13 ← (PC1L) || %00001000 || $08 ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR P, K || 1 || 4 || PC1U←(R12), PC1L←(R13) || %00001001 || $09 ||- ||- ||- ||-
+
| LR P, K || 1 || 4 || PC1U ← (R12), PC1L ← (R13) || %00001001 || $09 ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR A, IS || 1 || 1 || A←(ISAR) || %00001010 || $0A ||- ||- ||- ||-
+
| LR A, IS || 1 || 1 || A ← (ISAR) || %00001010 || $0A ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR IS, A || 1 || 1 || ISAR←(A) || %00001011 || $0B ||- ||- ||- ||-
+
| LR IS, A || 1 || 1 || ISAR ← (A) || %00001011 || $0B ||- ||- ||- ||-
 
|-  
 
|-  
−
| PK || 1 || 2.5 || PC1←(PC0), PC0L←(R13), PC0U←(R12) || %00001100 || $0C ||- ||- ||- ||-
+
| PK || 1 || 2.5 || PC1 ← (PC0), PC0L ← (R13), PC0U ← (R12) || %00001100 || $0C ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR P0, Q || 1 || 4 || PC0L←(R15), PC0U←(R14) || %00001101 || $0D ||- ||- ||- ||-
+
| LR P0, Q || 1 || 4 || PC0L ← (R15), PC0U ← (R14) || %00001101 || $0D ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR Q, DC || 1 || 4 || R14←(DC0U), R15←(DC0L) || %00001110 || $0E ||- ||- ||- ||-
+
| LR Q, DC || 1 || 4 || R14 ← (DC0U), R15 ← (DC0L) || %00001110 || $0E ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR DC, Q || 1 || 4 || DC0U←(R14), DC0L←(R15) || %00001111 || $0F ||- ||- ||- ||-
+
| LR DC, Q || 1 || 4 || DC0U ← (R14), DC0L ← (R15) || %00001111 || $0F ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR DC, H || 1 || 4 || DC0U←(R10), DC0L←(R11) || %00010000 || $10 ||- ||- ||- ||-
+
| LR DC, H || 1 || 4 || DC0U ← (R10), DC0L ← (R11) || %00010000 || $10 ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR H, DC || 1 || 4 || R10←(DC0U), R11←(DC0L) || %00010001 || $11 ||- ||- ||- ||-
+
| LR H, DC || 1 || 4 || R10 ← (DC0U), R11 ← (DC0L) || %00010001 || $11 ||- ||- ||- ||-
 
|-  
 
|-  
 
| SR 1 || 1 || 1 || Shift (A) right one bit, fill with %0 || %00010010 || $12 || 0 || X || 0 || 1
 
| SR 1 || 1 || 1 || Shift (A) right one bit, fill with %0 || %00010010 || $12 || 0 || X || 0 || 1
Line 124: Line 124:
 
| SL 4 || 1 || 1 || Shift (A) left four bits, fill with %0000 || %00010101 || $15 || 0 || X || 0 || X
 
| SL 4 || 1 || 1 || Shift (A) left four bits, fill with %0000 || %00010101 || $15 || 0 || X || 0 || X
 
|-  
 
|-  
−
| LM || 1 || 2.5 || A←((DC0)), DC0←DC0 + 1 || %00010110 || $16 ||- ||- ||- ||-
+
| LM || 1 || 2.5 || A ← ((DC0)), DC0 ← DC0 + 1 || %00010110 || $16 ||- ||- ||- ||-
 
|-  
 
|-  
−
| ST || 1 || 2.5 || DC0←(A), DC0←DC0 + 1 || %00010111 || $17 ||- ||- ||- ||-
+
| ST || 1 || 2.5 || DC0 ← (A), DC0 ← DC0 + 1 || %00010111 || $17 ||- ||- ||- ||-
 
|-
 
|-
−
| COM || 1 || 1 || A←(A)⊕$FF [invert/complement]|| %00011000 || $18 || 0 || X || 0 || X
+
| COM || 1 || 1 || A ← (A)⊕$FF [invert/complement]|| %00011000 || $18 || 0 || X || 0 || X
 
|-  
 
|-  
−
| LNK || 1 || 1 || A←(A)+(C) || %00011001 || $19 ||X ||X ||X ||X
+
| LNK || 1 || 1 || A ← (A)+(C) || %00011001 || $19 ||X ||X ||X ||X
 
|-  
 
|-  
 
| DI || 1 || 1 || Disable interrupts, status register bit 4 || %00011010 || $1A ||- ||- ||- ||-  
 
| DI || 1 || 1 || Disable interrupts, status register bit 4 || %00011010 || $1A ||- ||- ||- ||-  
Line 136: Line 136:
 
| EI || 1 || 1 || Enable interrupts, status register bit 4 || %00011011 || $1B ||- ||- ||- ||-  
 
| EI || 1 || 1 || Enable interrupts, status register bit 4 || %00011011 || $1B ||- ||- ||- ||-  
 
|-  
 
|-  
−
| POP || 1 || 2 || PC0←(PC1), A destroyed || %00011100 || $1C ||- ||- ||- ||-
+
| POP || 1 || 2 || PC0 ← (PC1), A destroyed || %00011100 || $1C ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR W, J || 1 || 1 || W←(R9) || %00011101 || $1D ||- ||- ||- ||-
+
| LR W, J || 1 || 1 || W ← (R9) || %00011101 || $1D ||- ||- ||- ||-
 
|-  
 
|-  
−
| LR J, W || 1 || 2 || R9←(W) || %00011110 || $1E ||- ||- ||- ||-
+
| LR J, W || 1 || 2 || R9 ← (W) || %00011110 || $1E ||- ||- ||- ||-
 
|-
 
|-
−
| INC || 1 || 1 || A←(A)+1 || %00011111 || $1F ||X ||X ||X ||X
+
| INC || 1 || 1 || A ← (A)+1 || %00011111 || $1F ||X ||X ||X ||X
 
|-  
 
|-  
−
| LI n || 2 || 2.5 || A←n || %00100000 %xxxxxxxx || $20 $xx ||- ||- ||- ||-
+
| LI n || 2 || 2.5 || A ← n || %00100000 %xxxxxxxx || $20 $xx ||- ||- ||- ||-
 
|-  
 
|-  
−
| NI n || 2 || 2.5 || A←(A) AND n || %00100001 %xxxxxxxx || $21 $xx ||0 ||X ||0 ||X
+
| NI n || 2 || 2.5 || A ← (A) AND n || %00100001 %xxxxxxxx || $21 $xx ||0 ||X ||0 ||X
 
|-  
 
|-  
−
| OI n || 2 || 2.5 || A←(A) OR n || %00100010 %xxxxxxxx || $22 $xx ||0 ||X ||0 ||X
+
| OI n || 2 || 2.5 || A ← (A) OR n || %00100010 %xxxxxxxx || $22 $xx ||0 ||X ||0 ||X
 
|-  
 
|-  
−
| XI n || 2 || 2.5 || A←(A)⊕n || %00100011 %xxxxxxxx || $23 $xx ||0 ||X ||0 ||X
+
| XI n || 2 || 2.5 || A ← (A)⊕n || %00100011 %xxxxxxxx || $23 $xx ||0 ||X ||0 ||X
 
|-  
 
|-  
−
| AI n || 2 || 2.5 || A←(A)+n || %00100100 %xxxxxxxx || $24 $xx || X || X || X || X
+
| AI n || 2 || 2.5 || A ← (A)+n || %00100100 %xxxxxxxx || $24 $xx || X || X || X || X
 
|-  
 
|-  
 
| CI n || 2 || 2.5 || n+!(A)+1 (n-A), Only set status || %00100101 %xxxxxxxx || $25 $xx ||X ||X ||X ||X
 
| CI n || 2 || 2.5 || n+!(A)+1 (n-A), Only set status || %00100101 %xxxxxxxx || $25 $xx ||X ||X ||X ||X
 
|-  
 
|-  
−
| IN n || 2 || 4 || Data Bus←Port n,  A←(Port n)|| %00100110 %xxxxxxxx || $26 $xx ||0 ||X ||0 ||X
+
| IN n || 2 || 4 || Data Bus ← Port n,  A ← (Port n)|| %00100110 %xxxxxxxx || $26 $xx ||0 ||X ||0 ||X
 
|-  
 
|-  
−
| OUT n || 2 || 4 || Data Bus←Port n, Port n←(A)|| %00100111 %xxxxxxxx || $27 $xx ||- ||- ||- ||-
+
| OUT n || 2 || 4 || Data Bus ← Port n, Port n ← (A)|| %00100111 %xxxxxxxx || $27 $xx ||- ||- ||- ||-
 
|-
 
|-
−
| PI mn|| 3 || 6.5 || A←m, PC1←(PC0)+1, PC0L←n, PC0U←(A) || %00101000 %xxxxxxxx %xxxxxxxx || $28 $xx $xx ||- ||- ||- ||-
+
| PI mn|| 3 || 6.5 || A ← m, PC1 ← (PC0)+1, PC0L ← n, PC0U ← (A) || %00101000 %xxxxxxxx %xxxxxxxx || $28 $xx $xx ||- ||- ||- ||-
 
|-  
 
|-  
−
| JMP mn || 3 || 5.5 || A←m, PC0L←n, PC0U←(A) [A is destroyed] || %00101001 %xxxxxxxx %xxxxxxxx || $29 $xx $xx ||- ||- ||- ||-
+
| JMP mn || 3 || 5.5 || A ← m, PC0L ← n, PC0U ← (A) [A is destroyed] || %00101001 %xxxxxxxx %xxxxxxxx || $29 $xx $xx ||- ||- ||- ||-
 
|-  
 
|-  
−
| DCI mn || 3 || 6 || DC0U←m, PC0++, DC0L←n, PC0=PC0+1 || %00101010 %xxxxxxxx %xxxxxxxx || $2A $xx $xx ||- ||- ||- ||-
+
| DCI mn || 3 || 6 || DC0U ← m, PC0++, DC0L ← n, PC0=PC0+1 || %00101010 %xxxxxxxx %xxxxxxxx || $2A $xx $xx ||- ||- ||- ||-
 
|-  
 
|-  
 
| NOP || 1 || 1 || No operation (cycle waster) || %00101011 || $2B ||- ||- ||- ||-  
 
| NOP || 1 || 1 || No operation (cycle waster) || %00101011 || $2B ||- ||- ||- ||-  
 
|-  
 
|-  
−
| XDC || 1 || 2 || DC0,DC1←DC1,DC0 || %00101100 || $2C ||- ||- ||- ||-
+
| XDC || 1 || 2 || DC0,DC1 ← DC1,DC0 || %00101100 || $2C ||- ||- ||- ||-
 
|-  
 
|-  
−
| DS r || 1 || 1.5 || r←(r)+$FF, [decrease scratchpad byte] || %0011xxxx || $3x ||X ||X ||X ||X
+
| DS r || 1 || 1.5 || r ← (r)+$FF, [decrease scratchpad byte] || %0011xxxx || $3x ||X ||X ||X ||X
 
|-  
 
|-  
−
| LR A, r || 1 || 1 || A←(r) || %0100xxxx || $4x || - || - || - || -
+
| LR A, r || 1 || 1 || A ← (r) || %0100xxxx || $4x || - || - || - || -
 
|-  
 
|-  
−
| LR r, A || 1 || 1 || r←(A) || %0101xxxx || $5x ||- ||- ||- ||-
+
| LR r, A || 1 || 1 || r ← (A) || %0101xxxx || $5x ||- ||- ||- ||-
 
|-  
 
|-  
−
| LISU i || 1 || 1 || ISARU←i || %01100xxx || $6x ||- ||- ||- ||-
+
| LISU i || 1 || 1 || ISARU ← i || %01100xxx || $6x ||- ||- ||- ||-
 
|-  
 
|-  
−
| LISL i || 1 || 1 || ISARL←i || %01101xxx || $6x ||- ||- ||- ||-
+
| LISL i || 1 || 1 || ISARL ← i || %01101xxx || $6x ||- ||- ||- ||-
 
|-  
 
|-  
 
| CLR || 1 || 1 || A = 0 || %01110000 || $70 ||- ||- ||- ||-
 
| CLR || 1 || 1 || A = 0 || %01110000 || $70 ||- ||- ||- ||-
 
|-  
 
|-  
−
| LIS i || 1 || 1 || A←i || %0111xxxx || $7x ||- ||- ||- ||-
+
| LIS i || 1 || 1 || A ← i || %0111xxxx || $7x ||- ||- ||- ||-
 
|-  
 
|-  
 
| BT t, n || 2 || 3 (no branch)<br />3.5 (branch) || AND [[bitmask]] t with W, if result is not 0: P0 = P0 + 1 + n || %10000xxx %xxxxxxxx || $8x ||- ||- ||- ||-
 
| BT t, n || 2 || 3 (no branch)<br />3.5 (branch) || AND [[bitmask]] t with W, if result is not 0: P0 = P0 + 1 + n || %10000xxx %xxxxxxxx || $8x ||- ||- ||- ||-
Line 192: Line 192:
 
| BZ n || 2 || 3 (no branch)<br />3.5 (branch) || if ZERO: P0 = P0 + 1 + n || %10000100 %xxxxxxxx || $84 $xx ||- ||- ||- ||-  
 
| BZ n || 2 || 3 (no branch)<br />3.5 (branch) || if ZERO: P0 = P0 + 1 + n || %10000100 %xxxxxxxx || $84 $xx ||- ||- ||- ||-  
 
|-
 
|-
−
| AM || 1 || 2.5 || A&larr;(A)+((DC0)), DC0++ || %10001000 || $88 ||X ||X ||X ||X
+
| AM || 1 || 2.5 || A &larr; (A)+((DC0)), DC0++ || %10001000 || $88 ||X ||X ||X ||X
 
|-
 
|-
−
| AMD || 1 || 2.5 || A&larr;(A)+((DC0)) decimal adjusted, DC0++ || %10001001 || $89 ||X ||X ||X ||X
+
| AMD || 1 || 2.5 || A &larr; (A)+((DC0)) decimal adjusted, DC0++ || %10001001 || $89 ||X ||X ||X ||X
 
|-
 
|-
−
| NM || 1 || 2.5 || A&larr;(A)AND((DC0)),DC0++ || %10001010 || $8A ||0 ||X ||0 ||X
+
| NM || 1 || 2.5 || A &larr; (A)AND((DC0)),DC0++ || %10001010 || $8A ||0 ||X ||0 ||X
 
|-
 
|-
−
| OM || 1 || 2.5 || A&larr;(A)OR((DC0)),DC0++ || %10001011 || $8B ||0 ||X ||0 ||X
+
| OM || 1 || 2.5 || A &larr; (A)OR((DC0)),DC0++ || %10001011 || $8B ||0 ||X ||0 ||X
 
|-
 
|-
−
| XM || 1 || 2.5 || A&larr;(A)&oplus;((DC0)),DC0++ || %10001100 || $8C ||0 ||X ||0 ||X
+
| XM || 1 || 2.5 || A &larr; (A)&oplus;((DC0)),DC0++ || %10001100 || $8C ||0 ||X ||0 ||X
 
|-
 
|-
 
| CM || 1 || 2.5 || ((DC0))-A only set status, DC0++|| %10001101 || $8D ||X ||X ||X ||X
 
| CM || 1 || 2.5 || ((DC0))-A only set status, DC0++|| %10001101 || $8D ||X ||X ||X ||X
 
|-  
 
|-  
−
| ADC || 1 || 2.5 || DC0&larr;(DC0)+(A) || %10001110 || $8E ||- ||- ||- ||-
+
| ADC || 1 || 2.5 || DC0 &larr; (DC0)+(A) || %10001110 || $8E ||- ||- ||- ||-
 
|-  
 
|-  
−
| BR7 n || 2 || 2 (no branch)<br />2.5 (branch) || if ISARL != 7: PC0&larr;(PC0) + n +1 || %10001111 %xxxxxxxx || $8F $xx ||- ||- ||- ||-
+
| BR7 n || 2 || 2 (no branch)<br />2.5 (branch) || if ISARL != 7: PC0 &larr; (PC0) + n +1 || %10001111 %xxxxxxxx || $8F $xx ||- ||- ||- ||-
 
|-
 
|-
−
| BR n || 2 || 3.5 || PC0&larr;(PC0)+n+1 || %10010000 %xxxxxxxx || $90 $xx ||- ||- ||- ||-  
+
| BR n || 2 || 3.5 || PC0 &larr; (PC0)+n+1 || %10010000 %xxxxxxxx || $90 $xx ||- ||- ||- ||-  
 
|-  
 
|-  
−
| BF i, n || 2 || 3 (no branch)<br />3.5 (branch) || AND [[bitmask]] i with W, if result = FALSE: PC0&larr;(PC0)+n+1 || %1001xxxx %xxxxxxxx || $9x ||- ||- ||- ||-
+
| BF i, n || 2 || 3 (no branch)<br />3.5 (branch) || AND [[bitmask]] i with W, if result = FALSE: PC0 &larr; (PC0)+n+1 || %1001xxxx %xxxxxxxx || $9x ||- ||- ||- ||-
 
|-  
 
|-  
−
| BM n || 2 || 3 (no branch)<br />3.5 (branch) || if [[Negative|NEGATIVE]]: PC0&larr;(PC0)+n+1 || %10010001 %xxxxxxxx || $91 $xx ||- ||- ||- ||-  
+
| BM n || 2 || 3 (no branch)<br />3.5 (branch) || if [[Negative|NEGATIVE]]: PC0 &larr; (PC0)+n+1 || %10010001 %xxxxxxxx || $91 $xx ||- ||- ||- ||-  
 
|-  
 
|-  
−
| BNC n || 2 || 3 (no branch)<br />3.5 (branch) || if NO CARRY: PC0&larr;(PC0)+n+1 || %10010010 %xxxxxxxx || $92 $xx ||- ||- ||- ||-
+
| BNC n || 2 || 3 (no branch)<br />3.5 (branch) || if NO CARRY: PC0 &larr; (PC0)+n+1 || %10010010 %xxxxxxxx || $92 $xx ||- ||- ||- ||-
 
|-  
 
|-  
−
| BNZ n || 2 || 3 (no branch)<br />3.5 (branch) || if NOT ZERO: PC0&larr;(PC0)+n+1 || %10010100 %xxxxxxxx || $94 $xx ||- ||- ||- ||-  
+
| BNZ n || 2 || 3 (no branch)<br />3.5 (branch) || if NOT ZERO: PC0 &larr; (PC0)+n+1 || %10010100 %xxxxxxxx || $94 $xx ||- ||- ||- ||-  
 
|-  
 
|-  
−
| BNO n || 2 || 3 (no branch)<br />3.5 (branch) || if NO OVERFLOW: PC0&larr;(PC0)+n+1 || %10011000 %xxxxxxxx || $98 $xx ||- ||- ||- ||-  
+
| BNO n || 2 || 3 (no branch)<br />3.5 (branch) || if NO OVERFLOW: PC0 &larr; (PC0)+n+1 || %10011000 %xxxxxxxx || $98 $xx ||- ||- ||- ||-  
 
|-  
 
|-  
−
| INS i || 1 || 2 (i=0-1)<br />4 (i=2-15) || A&larr;(Port i), if i=2-15: Data Bus&larr;Port Address, A&larr;(Port i) || %1010xxxx || $Ax ||0 ||X ||0 ||X
+
| INS i || 1 || 2 (i=0-1)<br />4 (i=2-15) || A &larr; (Port i), if i=2-15: Data Bus &larr; Port Address, A &larr; (Port i) || %1010xxxx || $Ax ||0 ||X ||0 ||X
 
|-  
 
|-  
−
| OUTS i || 1 || 2 (i=0-1)<br />4 (i=2-15) || Port i&larr;(A), if i=2-15: Data Bus&larr;Port Address, Port i&larr;(A) || %1011xxxx || $Bx ||- ||- ||- ||-
+
| OUTS i || 1 || 2 (i=0-1)<br />4 (i=2-15) || Port i &larr; (A), if i=2-15: Data Bus &larr; Port Address, Port i &larr; (A) || %1011xxxx || $Bx ||- ||- ||- ||-
 
|-  
 
|-  
−
| AS r || 1 || 1 || A&larr;(A)+(r) || %1100xxxx || $Cx || X || X || X || X
+
| AS r || 1 || 1 || A &larr; (A)+(r) || %1100xxxx || $Cx || X || X || X || X
 
|-
 
|-
−
| ASD r || 1 || 2 || A&larr;(A)+(r) (decimal) || %1101xxxx || $Dx ||X ||X ||X ||X
+
| ASD r || 1 || 2 || A &larr; (A)+(r) (decimal) || %1101xxxx || $Dx ||X ||X ||X ||X
 
|-
 
|-
−
| XS r || 1 || 1 || A&larr;(A)&oplus;(r) || %1110xxxx || $Ex ||0 ||X ||0 ||X
+
| XS r || 1 || 1 || A &larr; (A)&oplus;(r) || %1110xxxx || $Ex ||0 ||X ||0 ||X
 
|-
 
|-
−
| NS r || 1 || 1 || A&larr;(A)AND(r) || %1111xxxx || $Fx ||0 ||X ||0 ||X
+
| NS r || 1 || 1 || A &larr; (A)AND(r) || %1111xxxx || $Fx ||0 ||X ||0 ||X
 
|-
 
|-
−
|  || IRQ || 5.5 || PC0L&larr;Int address(l), PC0U&larr;Int.Address(u), PC1<-PC0 ||  ||  ||- ||- ||- ||-
+
|  || IRQ || 5.5 || PC0L &larr; Int address(l), PC0U &larr; Int.Address(u), PC1<-PC0 ||  ||  ||- ||- ||- ||-
 
|-
 
|-
−
|  || RESET || 3.5 || PC0&larr;0, PC1&larr;PC0 || || ||- ||- ||- ||-
+
|  || RESET || 3.5 || PC0 &larr; 0, PC1 &larr; PC0 || || ||- ||- ||- ||-
 
|}
 
|}

Revision as of 16:18, 8 September 2016

The CPU of a digital computer responds to a series of ones and zeros read from memory. The pattern of these that determine what the CPU is supposed to do are called Operation Codes or opcode. As an example the opcode $2B on the F8 System means No Operation (NOP). Programs are made up of opcodes which instruct the F8 System to do something, such as load a register with a value, perform arithmetic on a register, change the program counter (jump) or input or output data through the ports. Opcodes in the F8 System are each one byte wide, though some may be followed by an address (two bytes) or a value for the opcode to use, these extra bytes are called operands and an opcode with its operand is called an instruction and the complete set for a CPU is called an Instruction Set. Instead of programming these numbers directly (Machine Code Programming) programmers came up with the mnemonic names and wrote programs to translate such code into machine code. This mnemonic form of programming is called Assembly Language. Below is a table showing both types, if you choose Assembly Language then DASM or f8tool are free Assemblers for the F8 System.

The Instruction Set

In the information for each opcode, the following notations are used:

Opcode Notations
A Accumulator
Ri Scratchpad register i (r0-r11)
P0 Program counter
P Program counter Stack
DC0 Data counter
DC1 Alternate data counter
W Status register
ISAR Indirect Scratchpad Address Register
r Scratchpad addressing as:
0 to 11 Select registers r0-r11
I Select ISAR, then ISAR = ISAR + 1
S Select ISAR
D Select ISAR, then ISAR = ISAR - 1
t 3-bit constant
i 4-bit constant
n 8-bit constant
mn 16-bit constant
( ) Contents of memory (e.g., (DC))
x Binary value placeholder
Status Flag Notations
O Overflow Flag
Z Zero Flag
C Carry Flag
S Sign Flag
0 Resets status flag
1 Sets status flag
X Modifies status flag
Table copied from F8_info
Extra data added from L. Turner F8 ins
As well as the excellent User's Guide (1976)
Mnemonic Length Cycles Description Opcode Status Flags
Binary Hex O Z C S
LR A, Ku 1 1 A ← (R12)  %00000000 $00 - - - -
LR A, Kl 1 1 A ← (R13)  %00000001 $01 - - - -
LR A, Qu 1 1 A ← (R14)  %00000010 $02 - - - -
LR A, Ql 1 1 A ← (R15)  %00000011 $03 - - - -
LR Ku, A 1 1 R12 ← (A)  %00000100 $04 - - - -
LR Kl, A 1 1 R13 ← (A)  %00000101 $05 - - - -
LR Qu, A 1 1 R14 ← (A)  %00000110 $06 - - - -
LR Ql, A 1 1 R15 ← (A)  %00000111 $07 - - - -
LR K, P 1 4 R12 ← (PC1U), R13 ← (PC1L)  %00001000 $08 - - - -
LR P, K 1 4 PC1U ← (R12), PC1L ← (R13)  %00001001 $09 - - - -
LR A, IS 1 1 A ← (ISAR)  %00001010 $0A - - - -
LR IS, A 1 1 ISAR ← (A)  %00001011 $0B - - - -
PK 1 2.5 PC1 ← (PC0), PC0L ← (R13), PC0U ← (R12)  %00001100 $0C - - - -
LR P0, Q 1 4 PC0L ← (R15), PC0U ← (R14)  %00001101 $0D - - - -
LR Q, DC 1 4 R14 ← (DC0U), R15 ← (DC0L)  %00001110 $0E - - - -
LR DC, Q 1 4 DC0U ← (R14), DC0L ← (R15)  %00001111 $0F - - - -
LR DC, H 1 4 DC0U ← (R10), DC0L ← (R11)  %00010000 $10 - - - -
LR H, DC 1 4 R10 ← (DC0U), R11 ← (DC0L)  %00010001 $11 - - - -
SR 1 1 1 Shift (A) right one bit, fill with %0  %00010010 $12 0 X 0 1
SL 1 1 1 Shift (A) left one bit, fill with %0  %00010011 $13 0 X 0 X
SR 4 1 1 Shift (A) right four bits, fill with %0000  %00010100 $14 0 X 0 1
SL 4 1 1 Shift (A) left four bits, fill with %0000  %00010101 $15 0 X 0 X
LM 1 2.5 A ← ((DC0)), DC0 ← DC0 + 1  %00010110 $16 - - - -
ST 1 2.5 DC0 ← (A), DC0 ← DC0 + 1  %00010111 $17 - - - -
COM 1 1 A ← (A)⊕$FF [invert/complement]  %00011000 $18 0 X 0 X
LNK 1 1 A ← (A)+(C)  %00011001 $19 X X X X
DI 1 1 Disable interrupts, status register bit 4  %00011010 $1A - - - -
EI 1 1 Enable interrupts, status register bit 4  %00011011 $1B - - - -
POP 1 2 PC0 ← (PC1), A destroyed  %00011100 $1C - - - -
LR W, J 1 1 W ← (R9)  %00011101 $1D - - - -
LR J, W 1 2 R9 ← (W)  %00011110 $1E - - - -
INC 1 1 A ← (A)+1  %00011111 $1F X X X X
LI n 2 2.5 A ← n  %00100000 %xxxxxxxx $20 $xx - - - -
NI n 2 2.5 A ← (A) AND n  %00100001 %xxxxxxxx $21 $xx 0 X 0 X
OI n 2 2.5 A ← (A) OR n  %00100010 %xxxxxxxx $22 $xx 0 X 0 X
XI n 2 2.5 A ← (A)⊕n  %00100011 %xxxxxxxx $23 $xx 0 X 0 X
AI n 2 2.5 A ← (A)+n  %00100100 %xxxxxxxx $24 $xx X X X X
CI n 2 2.5 n+!(A)+1 (n-A), Only set status  %00100101 %xxxxxxxx $25 $xx X X X X
IN n 2 4 Data Bus ← Port n, A ← (Port n)  %00100110 %xxxxxxxx $26 $xx 0 X 0 X
OUT n 2 4 Data Bus ← Port n, Port n ← (A)  %00100111 %xxxxxxxx $27 $xx - - - -
PI mn 3 6.5 A ← m, PC1 ← (PC0)+1, PC0L ← n, PC0U ← (A)  %00101000 %xxxxxxxx %xxxxxxxx $28 $xx $xx - - - -
JMP mn 3 5.5 A ← m, PC0L ← n, PC0U ← (A) [A is destroyed]  %00101001 %xxxxxxxx %xxxxxxxx $29 $xx $xx - - - -
DCI mn 3 6 DC0U ← m, PC0++, DC0L ← n, PC0=PC0+1  %00101010 %xxxxxxxx %xxxxxxxx $2A $xx $xx - - - -
NOP 1 1 No operation (cycle waster)  %00101011 $2B - - - -
XDC 1 2 DC0,DC1 ← DC1,DC0  %00101100 $2C - - - -
DS r 1 1.5 r ← (r)+$FF, [decrease scratchpad byte]  %0011xxxx $3x X X X X
LR A, r 1 1 A ← (r)  %0100xxxx $4x - - - -
LR r, A 1 1 r ← (A)  %0101xxxx $5x - - - -
LISU i 1 1 ISARU ← i  %01100xxx $6x - - - -
LISL i 1 1 ISARL ← i  %01101xxx $6x - - - -
CLR 1 1 A = 0  %01110000 $70 - - - -
LIS i 1 1 A ← i  %0111xxxx $7x - - - -
BT t, n 2 3 (no branch)
3.5 (branch) 		AND bitmask t with W, if result is not 0: P0 = P0 + 1 + n  %10000xxx %xxxxxxxx $8x - - - -
BP n 2 3 (no branch)
3.5 (branch) 		if POSITIVE: P0 = P0 + 1 + n  %10000001 %xxxxxxxx $81 $xx - - - -
BC n 2 3 (no branch)
3.5 (branch) 		if CARRY: P0 = P0 + 1 + n  %10000010 %xxxxxxxx $82 $xx - - - -
BZ n 2 3 (no branch)
3.5 (branch) 		if ZERO: P0 = P0 + 1 + n  %10000100 %xxxxxxxx $84 $xx - - - -
AM 1 2.5 A ← (A)+((DC0)), DC0++  %10001000 $88 X X X X
AMD 1 2.5 A ← (A)+((DC0)) decimal adjusted, DC0++  %10001001 $89 X X X X
NM 1 2.5 A ← (A)AND((DC0)),DC0++  %10001010 $8A 0 X 0 X
OM 1 2.5 A ← (A)OR((DC0)),DC0++  %10001011 $8B 0 X 0 X
XM 1 2.5 A ← (A)⊕((DC0)),DC0++  %10001100 $8C 0 X 0 X
CM 1 2.5 ((DC0))-A only set status, DC0++  %10001101 $8D X X X X
ADC 1 2.5 DC0 ← (DC0)+(A)  %10001110 $8E - - - -
BR7 n 2 2 (no branch)
2.5 (branch) 		if ISARL != 7: PC0 ← (PC0) + n +1  %10001111 %xxxxxxxx $8F $xx - - - -
BR n 2 3.5 PC0 ← (PC0)+n+1  %10010000 %xxxxxxxx $90 $xx - - - -
BF i, n 2 3 (no branch)
3.5 (branch) 		AND bitmask i with W, if result = FALSE: PC0 ← (PC0)+n+1  %1001xxxx %xxxxxxxx $9x - - - -
BM n 2 3 (no branch)
3.5 (branch) 		if NEGATIVE: PC0 ← (PC0)+n+1  %10010001 %xxxxxxxx $91 $xx - - - -
BNC n 2 3 (no branch)
3.5 (branch) 		if NO CARRY: PC0 ← (PC0)+n+1  %10010010 %xxxxxxxx $92 $xx - - - -
BNZ n 2 3 (no branch)
3.5 (branch) 		if NOT ZERO: PC0 ← (PC0)+n+1  %10010100 %xxxxxxxx $94 $xx - - - -
BNO n 2 3 (no branch)
3.5 (branch) 		if NO OVERFLOW: PC0 ← (PC0)+n+1  %10011000 %xxxxxxxx $98 $xx - - - -
INS i 1 2 (i=0-1)
4 (i=2-15) 		A ← (Port i), if i=2-15: Data Bus ← Port Address, A ← (Port i)  %1010xxxx $Ax 0 X 0 X
OUTS i 1 2 (i=0-1)
4 (i=2-15) 		Port i ← (A), if i=2-15: Data Bus ← Port Address, Port i ← (A)  %1011xxxx $Bx - - - -
AS r 1 1 A ← (A)+(r)  %1100xxxx $Cx X X X X
ASD r 1 2 A ← (A)+(r) (decimal)  %1101xxxx $Dx X X X X
XS r 1 1 A ← (A)⊕(r)  %1110xxxx $Ex 0 X 0 X
NS r 1 1 A ← (A)AND(r)  %1111xxxx $Fx 0 X 0 X
IRQ 5.5 PC0L ← Int address(l), PC0U ← Int.Address(u), PC1<-PC0 - - - -
RESET 3.5 PC0 ← 0, PC1 ← PC0 - - - -
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