Difference between revisions of "Opcode"

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(→‎The BF instruction)
(→‎The Instruction Set)
 
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Line 22: Line 22:
 
|-  
 
|-  
 
| '''W''' || [[Status register]] (x,x,x,ICB,O,Z,C,S) Exhange only via<br>the '''J''' register (R9)
 
| '''W''' || [[Status register]] (x,x,x,ICB,O,Z,C,S) Exhange only via<br>the '''J''' register (R9)
 +
|-
 +
! colspan="2" | Register alias
 +
|-
 +
| || '''HU''' = ISAR r10, '''HL''' = ISAR r11<br>'''KU''' = ISAR r12, '''KL''' = ISAR r13<br>'''QU''' = ISAR r14, '''QL''' = ISAR r15
 
|-  
 
|-  
 
| '''ISAR''' || [[ISAR|Indirect Scratchpad Address Register]]
 
| '''ISAR''' || [[ISAR|Indirect Scratchpad Address Register]]
 
|-  
 
|-  
−
| '''r''' || Scratchpad addressing as:
+
| '''r''' || Scratchpad addressing ONLY as:
 
{| border="1" cellspacing="1" cellpadding="4"
 
{| border="1" cellspacing="1" cellpadding="4"
  
−
| '''0 to 11''' || Select registers r0-r11
+
| '''0 to 11''' || ISAR registers r0-r11
 
|-  
 
|-  
−
| '''12''', '''S''' or '''IS''' || Reg. selected by ISAR <br> '''You can't call r12 (KU) using register number'''
+
| '''S''' not preferred: '''(IS)''' || Reg. selected by ISAR <br> '''You can't call r12 (KU) using register number'''
 
|-  
 
|-  
−
| '''13''', '''I''' or '''(IS)+''' || Reg. selected by ISAR, then ISAR = ISAR + 1 <br> '''You can't call r13 (KL) using register number'''  
+
| '''I''' not preferred: '''(IS)+''' || Reg. selected by ISAR, then (ISAR)++ <br> '''You can't call r13 (KL) using register number'''  
 
|-  
 
|-  
−
| '''14''', '''D''' or '''(IS)-'''  || Reg. selected by ISAR, then ISAR = ISAR - 1 <br> '''You can't call r14 (QU) using register number'''
+
| '''D''' not preferred: '''(IS)-'''  || Reg. selected by ISAR, then (ISAR)-- <br> '''You can't call r14 (QU) using register number'''
 
|}
 
|}
 
|-  
 
|-  
Line 86: Line 90:
 
! style="width: 1.5em; cursor: help" title="Signed" | S
 
! style="width: 1.5em; cursor: help" title="Signed" | S
 
|-  
 
|-  
−
| LR A, KU || 1 || 1 || A &larr; (KU)[r12] || %00000000 || $00 ||- ||- ||- ||- || S || 0
+
| LR A, KU || 1 || 1 || A &larr; (KU) || %00000000 || $00 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR A, KL || 1 || 1 || A &larr; (KL)[r13] || %00000001 || $01 ||- ||- ||- ||- || S || 0
+
| LR A, KL || 1 || 1 || A &larr; (KL) || %00000001 || $01 ||- ||- ||- ||- || S || 0
 
|- =  
 
|- =  
−
| LR A, QU || 1 || 1 || A &larr; (QU)[r14]|| %00000010 || $02 ||- ||- ||- ||- || S || 0
+
| LR A, QU || 1 || 1 || A &larr; (QU) || %00000010 || $02 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR A, QL || 1 || 1 || A &larr; (QL)[r15]|| %00000011 || $03 ||- ||- ||- ||- || S || 0
+
| LR A, QL || 1 || 1 || A &larr; (QL) || %00000011 || $03 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR KU, A || 1 || 1 || [r12]KU &larr; (A) || %00000100 || $04 ||- ||- ||- ||- || S || 0
+
| LR KU, A || 1 || 1 || KU &larr; (A) || %00000100 || $04 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR KL, A || 1 || 1 || [r13]KL &larr; (A) || %00000101 || $05 ||- ||- ||- ||- || S || 0
+
| LR KL, A || 1 || 1 || KL &larr; (A) || %00000101 || $05 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR QU, A || 1 || 1 || [r14]QU &larr; (A) || %00000110 || $06 ||- ||- ||- ||- || S || 0
+
| LR QU, A || 1 || 1 || QU &larr; (A) || %00000110 || $06 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR QL, A || 1 || 1 || [r15]QL &larr; (A) || %00000111 || $07 ||- ||- ||- ||- || S || 0
+
| LR QL, A || 1 || 1 || QL &larr; (A) || %00000111 || $07 ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| LR K, P || 1 || 4 || [r12]KU &larr; (PC1U)<br>[r13]KL &larr; (PC1L) || %00001000 || $08 ||- ||- ||- ||- || L <br> L <br> S || 7 <br> B <br> 0
+
| LR K, P || 1 || 4 || KU &larr; (PC1U)<br>KL &larr; (PC1L) || %00001000 || $08 ||- ||- ||- ||- || L <br> L <br> S || 7 <br> B <br> 0
 
|-  
 
|-  
−
| LR P, K || 1 || 4 || PC1U &larr; (KU)[r12] <br>PC1L &larr; (KL)[r13] || %00001001 || $09 ||- ||- ||- ||- || L <br> L <br> S || 15 <br> 18 <br> 0
+
| LR P, K || 1 || 4 || PC1U &larr; (KU) <br>PC1L &larr; (KL) || %00001001 || $09 ||- ||- ||- ||- || L <br> L <br> S || 15 <br> 18 <br> 0
 
|-  
 
|-  
 
| LR A, IS || 1 || 1 || A &larr; (ISAR) || %00001010 || $0A ||- ||- ||- ||- || S || 0
 
| LR A, IS || 1 || 1 || A &larr; (ISAR) || %00001010 || $0A ||- ||- ||- ||- || S || 0
Line 110: Line 114:
 
| LR IS, A || 1 || 1 || ISAR &larr; (A) || %00001011 || $0B ||- ||- ||- ||- || S || 0
 
| LR IS, A || 1 || 1 || ISAR &larr; (A) || %00001011 || $0B ||- ||- ||- ||- || S || 0
 
|-  
 
|-  
−
| PK || 1 || 2.5 || PC1 &larr; (PC0)<br>PC0L &larr; (KL)[r13]<br>PC0U &larr; (KU)[r12] || %00001100 || $0C ||- ||- ||- ||- || L <br> L <br> S || 12 <br> 14 <br> 0
+
| PK || 1 || 2.5 || PC1 &larr; (PC0)<br>PC0L &larr; (KL)<br>PC0U &larr; (KU) || %00001100 || $0C ||- ||- ||- ||- || L <br> L <br> S || 12 <br> 14 <br> 0
 
|-  
 
|-  
−
| LR P0, Q || 1 || 4 || PC0L &larr; (QL)[r15]<br>PC0U &larr; (QU)[r14] || %00001101 || $0D ||- ||- ||- ||- || L <br> L <br> S || 17 <br> 14 <br> 0
+
| LR P0, Q || 1 || 4 || PC0L &larr; (QL)<br>PC0U &larr; (QU) || %00001101 || $0D ||- ||- ||- ||- || L <br> L <br> S || 17 <br> 14 <br> 0
 
|-  
 
|-  
−
| LR Q, DC || 1 || 4 || [r14]QU &larr; (DC0U)<br>[r15]QL &larr; (DC0L) || %00001110 || $0E ||- ||- ||- ||- || L <br> L <br> S || 6 <br> 9 <br> 0
+
| LR Q, DC || 1 || 4 || QU &larr; (DC0U)<br>QL &larr; (DC0L) || %00001110 || $0E ||- ||- ||- ||- || L <br> L <br> S || 6 <br> 9 <br> 0
 
|-  
 
|-  
−
| LR DC, Q || 1 || 4 || DC0U &larr; (QU)[r14]<br>DC0L &larr; (QL)[r15] || %00001111 || $0F ||- ||- ||- ||- || L <br> L <br> S || 16 <br> 19 <br> 0
+
| LR DC, Q || 1 || 4 || DC0U &larr; (QU)<br>DC0L &larr; (QL) || %00001111 || $0F ||- ||- ||- ||- || L <br> L <br> S || 16 <br> 19 <br> 0
 
|-  
 
|-  
−
| LR DC, H || 1 || 4 || DC0U &larr; (R10)<br>DC0L &larr; (R11) || %00010000 || $10 ||- ||- ||- ||- || L <br> L <br> S || 16 <br> 19 <br> 0
+
| LR DC, H || 1 || 4 || DC0U &larr; (HU)<br>DC0L &larr; (HL) || %00010000 || $10 ||- ||- ||- ||- || L <br> L <br> S || 16 <br> 19 <br> 0
 
|-  
 
|-  
−
| LR H, DC || 1 || 4 || R10 &larr; (DC0U)<br>R11 &larr; (DC0L) || %00010001 || $11 ||- ||- ||- ||- || L <br> L <br> S || 6 <br> 9 <br> 0
+
| LR H, DC || 1 || 4 || HU &larr; (DC0U)<br>HL &larr; (DC0L) || %00010001 || $11 ||- ||- ||- ||- || L <br> L <br> S || 6 <br> 9 <br> 0
 
|-  
 
|-  
 
| SR 1 || 1 || 1 || Shift (A) right one bit, fill with %0 || %00010010 || $12 || 0 || X || 0 || 1 || S || 0
 
| SR 1 || 1 || 1 || Shift (A) right one bit, fill with %0 || %00010010 || $12 || 0 || X || 0 || 1 || S || 0
Line 168: Line 172:
 
| PI mn|| 3 || 6.5 || A &larr; m<br>PC1 &larr; (PC0)+1<br>PC0L &larr; n<br>PC0U &larr; (A)<br>[A is destroyed] || %00101000 %xxxxxxxx %xxxxxxxx || $28 $xx $xx ||- ||- ||- ||- || L <br> S <br> L <br> L <br> S || 3 <br> D <br> C <br> 14 <br> 0
 
| PI mn|| 3 || 6.5 || A &larr; m<br>PC1 &larr; (PC0)+1<br>PC0L &larr; n<br>PC0U &larr; (A)<br>[A is destroyed] || %00101000 %xxxxxxxx %xxxxxxxx || $28 $xx $xx ||- ||- ||- ||- || L <br> S <br> L <br> L <br> S || 3 <br> D <br> C <br> 14 <br> 0
 
|-  
 
|-  
−
| JMP mn || 3 || 5.5 || A &larr; m<br>PC0L &larr; n<br>PC0U &larr; (A)<br>[A is destroyed] || %00101001 %xxxxxxxx %xxxxxxxx || $29 $xx $xx ||- ||- ||- ||- || L <br> L <br> L <br> S || 3 <br> c <br> 14 <br> 0
+
| JMP mn || 3 || 5.5 || A &larr; m<br>PC0L &larr; n<br>PC0U &larr; (A)<br>[A now contains m] || %00101001 %xxxxxxxx %xxxxxxxx || $29 $xx $xx ||- ||- ||- ||- || L <br> L <br> L <br> S || 3 <br> c <br> 14 <br> 0
 
|-  
 
|-  
 
| DCI mn || 3 || 6 || DC0U &larr; m<br>PC0+1<br>DC0L &larr; n<br>PC0+1 || %00101010 %xxxxxxxx %xxxxxxxx || $2A $xx $xx ||- ||- ||- ||- || L <br> S <br> L <br> S <br> S || 11 <br> 3 <br> E <br> 3 <br> 0
 
| DCI mn || 3 || 6 || DC0U &larr; m<br>PC0+1<br>DC0L &larr; n<br>PC0+1 || %00101010 %xxxxxxxx %xxxxxxxx || $2A $xx $xx ||- ||- ||- ||- || L <br> S <br> L <br> S <br> S || 11 <br> 3 <br> E <br> 3 <br> 0
Line 221: Line 225:
 
| ADC || 1 || 2.5 || DC0 &larr; (DC0)+(A) || %10001110 || $8E ||- ||- ||- ||- || L <br> S || A <br> 0
 
| ADC || 1 || 2.5 || DC0 &larr; (DC0)+(A) || %10001110 || $8E ||- ||- ||- ||- || L <br> S || A <br> 0
 
|-  
 
|-  
−
| BR7 n || 2 || 2 (no branch)<br>2.5 (branch) || if ISARL != 7: PC0 &larr; (PC0) + n +1 || %10001111 %xxxxxxxx || $8F $xx ||- ||- ||- ||- || S <br> S <br> L <br> S || 3 <br> 0 <br> 1 <br> 0
+
| BR7 n || 2 || 2 (no branch)<br>2.5 (branch) || if (ISAR & 7)==7: PC0 &larr; (PC0) + n +1 || %10001111 %xxxxxxxx || $8F $xx ||- ||- ||- ||- || S <br> S <br> L <br> S || 3 <br> 0 <br> 1 <br> 0
 
|-
 
|-
 
| BR n || 2 || 3.5 || PC0 &larr; (PC0)+n+1 || %10010000 %xxxxxxxx || $90 $xx ||- ||- ||- ||-  ||  ||  
 
| BR n || 2 || 3.5 || PC0 &larr; (PC0)+n+1 || %10010000 %xxxxxxxx || $90 $xx ||- ||- ||- ||-  ||  ||  
Line 247: Line 251:
 
| NS r || 1 || 1 || A &larr; (A)AND(r) || %1111xxxx || $Fx ||0 ||X ||0 ||X || S || 0
 
| NS r || 1 || 1 || A &larr; (A)AND(r) || %1111xxxx || $Fx ||0 ||X ||0 ||X || S || 0
 
|-
 
|-
−
|  || IRQ || 5.5 || PC0L &larr; Int address(l)<br>PC0U &larr; Int.Address(u)<br>PC1<-PC0 ||  ||  ||- ||- ||- ||- || L <br> L <br> L <br> S || 1C <br> 0F <br> 13 <br> 0
+
|  || Hardware event: IRQ || 5.5 || PC0L &larr; Int address(l)<br>PC0U &larr; Int.Address(u)<br>PC1<-PC0 ||  ||  ||- ||- ||- ||- || L <br> L <br> L <br> S || 1C <br> 0F <br> 13 <br> 0
 
|-
 
|-
−
|  || RESET || 3.5 || PC0 &larr; 0<br>PC1 &larr; PC0 || || ||- ||- ||- ||- || S <br> L <br> S || 1C <br> 8 <br> 0
+
|  || Hardware event: RESET || 3.5 || PC0 &larr; 0<br>PC1 &larr; PC0 || || ||- ||- ||- ||- || S <br> L <br> S || 1C <br> 8 <br> 0
 
|}
 
|}
  

Latest revision as of 17:05, 16 June 2026

The CPU of a digital computer responds to a series of ones and zeros read from memory. The pattern of these, that determine what the CPU is supposed to do, are called Operation Codes or opcode. As an example the opcode $2B on the F8 System means No Operation (NOP). Programs are made up of opcodes which instruct the F8 System to do something, such as load a register with a value, perform arithmetic on a register, change the program counter (jump) or input or output data through the ports.
Opcodes in the F8 System are each one byte wide, though some may be followed by an address (two bytes) or a value for the opcode to use, these extra bytes are called operands and an opcode with its operand is called an instruction and the complete set for a CPU is called an Instruction Set.
Instead of programming these numbers directly (Machine Code Programming) programmers came up with the mnemonic names and wrote programs to translate such code into machine code. This mnemonic form of programming is called Assembly Language. Below is a table showing both types, if you choose Assembly Language then DASM or f8tool are free Assemblers for the F8 System.

The Instruction Set

In the information for each opcode, the following notations are used:

Opcode Notations
A Accumulator
Ri First registers i (r0-r11 [HU,HL=r10,11])
P0 Program counter (PC0)
P Program counter Stack (PC1)
DC0 Data counter
DC1 Data counter storage
W Status register (x,x,x,ICB,O,Z,C,S) Exhange only via
the J register (R9)
Register alias
HU = ISAR r10, HL = ISAR r11
KU = ISAR r12, KL = ISAR r13
QU = ISAR r14, QL = ISAR r15
ISAR Indirect Scratchpad Address Register
r Scratchpad addressing ONLY as:
0 to 11 ISAR registers r0-r11
S not preferred: (IS) Reg. selected by ISAR
You can't call r12 (KU) using register number
I not preferred: (IS)+ Reg. selected by ISAR, then (ISAR)++
You can't call r13 (KL) using register number
D not preferred: (IS)- Reg. selected by ISAR, then (ISAR)--
You can't call r14 (QU) using register number
t 3-bit constant
i 4-bit constant
n 8-bit constant
mn 16-bit constant
(  ) Contents of register (e.g.(R11) or (DC))
x Binary value placeholder
Status Flag Notations
ICB Interrupts Allowed Flag, b4 in W
O Overflow Flag, b3 in W
Z Zero Flag, b2 in W
C Carry Flag, b1 in W
S Sign Flag, b0 in W
0 Resets status flag
1 Sets status flag
X Modifies status flag
Table copied from F8_info
Extra data added from L. Turner F8 ins
As well as the excellent User's Guide (1976)
Mnemonic Length Cycles Description Opcode Status Flags Cycle ROMC
state
Binary Hex O Z C S
LR A, KU 1 1 A ← (KU)  %00000000 $00 - - - - S 0
LR A, KL 1 1 A ← (KL)  %00000001 $01 - - - - S 0
LR A, QU 1 1 A ← (QU)  %00000010 $02 - - - - S 0
LR A, QL 1 1 A ← (QL)  %00000011 $03 - - - - S 0
LR KU, A 1 1 KU ← (A)  %00000100 $04 - - - - S 0
LR KL, A 1 1 KL ← (A)  %00000101 $05 - - - - S 0
LR QU, A 1 1 QU ← (A)  %00000110 $06 - - - - S 0
LR QL, A 1 1 QL ← (A)  %00000111 $07 - - - - S 0
LR K, P 1 4 KU ← (PC1U)
KL ← (PC1L) 		 %00001000 $08 - - - - L
L
S 		7
B
0
LR P, K 1 4 PC1U ← (KU)
PC1L ← (KL) 		 %00001001 $09 - - - - L
L
S 		15
18
0
LR A, IS 1 1 A ← (ISAR)  %00001010 $0A - - - - S 0
LR IS, A 1 1 ISAR ← (A)  %00001011 $0B - - - - S 0
PK 1 2.5 PC1 ← (PC0)
PC0L ← (KL)
PC0U ← (KU) 		 %00001100 $0C - - - - L
L
S 		12
14
0
LR P0, Q 1 4 PC0L ← (QL)
PC0U ← (QU) 		 %00001101 $0D - - - - L
L
S 		17
14
0
LR Q, DC 1 4 QU ← (DC0U)
QL ← (DC0L) 		 %00001110 $0E - - - - L
L
S 		6
9
0
LR DC, Q 1 4 DC0U ← (QU)
DC0L ← (QL) 		 %00001111 $0F - - - - L
L
S 		16
19
0
LR DC, H 1 4 DC0U ← (HU)
DC0L ← (HL) 		 %00010000 $10 - - - - L
L
S 		16
19
0
LR H, DC 1 4 HU ← (DC0U)
HL ← (DC0L) 		 %00010001 $11 - - - - L
L
S 		6
9
0
SR 1 1 1 Shift (A) right one bit, fill with %0  %00010010 $12 0 X 0 1 S 0
SL 1 1 1 Shift (A) left one bit, fill with %0  %00010011 $13 0 X 0 X S 0
SR 4 1 1 Shift (A) right four bits, fill with %0000  %00010100 $14 0 X 0 1 S 0
SL 4 1 1 Shift (A) left four bits, fill with %0000  %00010101 $15 0 X 0 X S 0
LM 1 2.5 A ← ((DC0))
DC0 ← DC0 + 1 		 %00010110 $16 - - - - L
S 		2
0
ST 1 2.5 DC0 ← (A)
DC0 ← DC0 + 1 		 %00010111 $17 - - - - L
S 		5
0
COM 1 1 A ← (A)⊕$FF
[invert/complement]		  %00011000 $18 0 X 0 X S 0
LNK 1 1 A ← (A)+(C)
(add carry from previous operation)		  %00011001 $19 X X X X S 0
DI 1 1 Disable interrupts
status register bit 4 		 %00011010 $1A - - - - S
S 		1C
0
EI 1 1 Enable interrupts
status register bit 4 		 %00011011 $1B - - - - S
S 		1C
0
POP 1 2 PC0 ← (PC1)  %00011100 $1C - - - - S
S 		4
0
LR W, J 1 1 W ← (R9)  %00011101 $1D - - - - S
S 		1C
0
LR J, W 1 2 R9 ← (W)  %00011110 $1E - - - - S 0
INC 1 1 A ← (A)+1  %00011111 $1F X X X X S 0
LI n 2 2.5 A ← n  %00100000 %xxxxxxxx $20 $xx - - - - L
S 		3
0
NI n 2 2.5 A ← (A) AND n  %00100001 %xxxxxxxx $21 $xx 0 X 0 X L
S 		3
0
OI n 2 2.5 A ← (A) OR n  %00100010 %xxxxxxxx $22 $xx 0 X 0 X L
S 		3
0
XI n 2 2.5 A ← (A)⊕n  %00100011 %xxxxxxxx $23 $xx 0 X 0 X L
S 		3
0
AI n 2 2.5 A ← (A)+n  %00100100 %xxxxxxxx $24 $xx X X X X L
S 		3
0
CI n 2 2.5 n+!(A)+1 (n-A)
Only set status 		 %00100101 %xxxxxxxx $25 $xx X X X X L
S 		3
0
IN n 2 4 Data Bus ← Port n
A ← (Port n)		  %00100110 %xxxxxxxx $26 $xx 0 X 0 X L
L
S 		3
1B
0
OUT n 2 4 Data Bus ← Port n
Port n ← (A)		  %00100111 %xxxxxxxx $27 $xx - - - - L
L
S 		3
1A
0
PI mn 3 6.5 A ← m
PC1 ← (PC0)+1
PC0L ← n
PC0U ← (A)
[A is destroyed] 		 %00101000 %xxxxxxxx %xxxxxxxx $28 $xx $xx - - - - L
S
L
L
S 		3
D
C
14
0
JMP mn 3 5.5 A ← m
PC0L ← n
PC0U ← (A)
[A now contains m] 		 %00101001 %xxxxxxxx %xxxxxxxx $29 $xx $xx - - - - L
L
L
S 		3
c
14
0
DCI mn 3 6 DC0U ← m
PC0+1
DC0L ← n
PC0+1 		 %00101010 %xxxxxxxx %xxxxxxxx $2A $xx $xx - - - - L
S
L
S
S 		11
3
E
3
0
NOP 1 1 No operation
(cycle waster) 		 %00101011 $2B - - - - S 0
XDC 1 2 DC0,DC1 ← DC1,DC0  %00101100 $2C - - - - S
S 		1D
0
DS r 1 1.5 r ← (r)+$FF
[decrease scratchpad byte] 		 %0011xxxx $3x X X X X L 0
LR A, r 1 1 A ← (r)  %0100xxxx $4x - - - - S 0
LR A, HU 1 1 A ← (HU)  %01001010 $4A - - - - S 0
LR A, HL 1 1 A ← (HL)  %01001011 $4B - - - - S 0
LR r, A 1 1 r ← (A)  %0101xxxx $5x - - - - S 0
LR HU, A 1 1 HU ← (A)  %01011010 $5A - - - - S 0
LR HL, A 1 1 HL ← (A)  %01011011 $5B - - - - S 0
LISU i 1 1 ISARU ← i  %01100xxx $6x - - - - S 0
LISL i 1 1 ISARL ← i  %01101xxx $6x - - - - S 0
CLR 1 1 A←0  %01110000 $70 - - - - S 0
LIS i 1 1 A ← i  %0111xxxx $7x - - - - S 0
BT t, n 2 3 (no branch)
3.5 (branch) 		AND bitmask t with W
if result is not 0:
PC0←PC0+n+1
See table below 		 %10000xxx %xxxxxxxx $8x $xx - - - - S
S
S
S
L
S 		1C
3
0
1C
1
0
BP n 2 3 (no branch)
3.5 (branch) 		if POSITIVE
(sign bit 0):
PC0←PC0+n+1 		 %10000001 %xxxxxxxx $81 $xx - - - -
BC n 2 3 (no branch)
3.5 (branch) 		if CARRY:
PC0←PC0+n+1 		 %10000010 %xxxxxxxx $82 $xx - - - -
BZ n 2 3 (no branch)
3.5 (branch) 		if ZERO:
PC0←PC0+n+1 		 %10000100 %xxxxxxxx $84 $xx - - - -
AM 1 2.5 A ← (A)+((DC0))
DC0+1 		 %10001000 $88 X X X X L
S 		2
0
AMD 1 2.5 A ← (A)+((DC0))
decimal adjusted
DC0+1 		 %10001001 $89 X X X X L
S 		2
0
NM 1 2.5 A ← (A)AND((DC0))
DC0+1 		 %10001010 $8A 0 X 0 X L
S

2
0

OM 1 2.5 A ← (A)OR((DC0))
DC0+1 		 %10001011 $8B 0 X 0 X L
S 		2
0
XM 1 2.5 A ← (A)⊕((DC0))
DC0+1 		 %10001100 $8C 0 X 0 X L
S 		2
0
CM 1 2.5 ((DC0))-A only set status
DC0+1		  %10001101 $8D X X X X L
S 		2
0
ADC 1 2.5 DC0 ← (DC0)+(A)  %10001110 $8E - - - - L
S 		A
0
BR7 n 2 2 (no branch)
2.5 (branch) 		if (ISAR & 7)==7: PC0 ← (PC0) + n +1  %10001111 %xxxxxxxx $8F $xx - - - - S
S
L
S 		3
0
1
0
BR n 2 3.5 PC0 ← (PC0)+n+1  %10010000 %xxxxxxxx $90 $xx - - - -
BF i, n 2 3 (no branch)
3.5 (branch) 		AND bitmask i with W
if result = FALSE:
PC0 ← (PC0)+n+1
See table below 		 %1001xxxx %xxxxxxxx $9x $xx - - - - S
L
S
S
S
S		 1C
1
0
1C
3
0
BM n 2 3 (no branch)
3.5 (branch) 		if NEGATIVE:
PC0 ← (PC0)+n+1 		 %10010001 %xxxxxxxx $91 $xx - - - -
BNC n 2 3 (no branch)
3.5 (branch) 		if NO CARRY:
PC0 ← (PC0)+n+1 		 %10010010 %xxxxxxxx $92 $xx - - - -
BNZ n 2 3 (no branch)
3.5 (branch) 		if NOT ZERO:
PC0 ← (PC0)+n+1 		 %10010100 %xxxxxxxx $94 $xx - - - -
BNO n 2 3 (no branch)
3.5 (branch) 		if NO OVERFLOW:
PC0 ← (PC0)+n+1 		 %10011000 %xxxxxxxx $98 $xx - - - -
INS i 1 2 (i=0-1)
4 (i=2-15) 		A ← (Port i)
if i=2-15: Data Bus ← Port Address
A ← (Port i) 		 %1010xxxx $Ax 0 X 0 X p0/1: S, S
p4-F: L, L, S 		p0/1: 1C, 0
p4-F: 1C, 1B, 0
OUTS i 1 2 (i=0-1)
4 (i=2-15) 		Port i ← (A)
if i=2-15: Data Bus ← Port Address
Port i ← (A) 		 %1011xxxx $Bx - - - - p0/1: S, S
p4-F: L, L, S 		p0/1: 1C, 0
p4-F: 1C, 1A, 0
AS r 1 1 A ← (A)+(r)  %1100xxxx $Cx X X X X S 0
ASD r 1 2 A ← (A)+(r)
(decimal) 		 %1101xxxx $Dx X X X X S
S 		1C
0
XS r 1 1 A ← (A)⊕(r)  %1110xxxx $Ex 0 X 0 X S 0
NS r 1 1 A ← (A)AND(r)  %1111xxxx $Fx 0 X 0 X S 0
Hardware event: IRQ 5.5 PC0L ← Int address(l)
PC0U ← Int.Address(u)
PC1<-PC0 		- - - - L
L
L
S 		1C
0F
13
0
Hardware event: RESET 3.5 PC0 ← 0
PC1 ← PC0 		- - - - S
L
S 		1C
8
0


The BT instruction

Branch conditions for BT instruction
Operand
t 		Status flags tested
Definition
Comments
zero carry sign
0 0 0 0 Do not branch An effective 3
cycle NO-OP
1 0 0 1 Branch if Positive Same as BP
2 0 1 0 Branch on Carry Same as BC
3 0 1 1 Branch if Carry
or on Positive
4 1 0 0 Branch if Zero Same as BZ
5 1 0 1 Branch if Zero
or Positive 		Same as t=1
6 1 1 0 Branch if Zero or
on Carry
7 1 1 1 Branch if Zero,
Carry or Positive 		Same as t=3

The BF instruction

Branch conditions for BF instruction
Operand
t 		Status flags tested
Definition
Comments
 ovf  zero  carry sign 
0 0 0 0 0 Unconditional branch
relative 		Same as BR 
1 0 0 0 1 Branch on negative Same as BM 
2 0 0 1 0 Branch if no carry Same as BNC
3 0 0 1 1 Branch if no carry
and negative
4 0 1 0 0 Branch if not zero Same as BNZ
5 0 1 0 1 Same as t=1 
6 0 1 1 0 Branch if no carry
and not zero
7 0 1 1 1 Same as t=3 
8 1 0 0 0 Branch if there is no
overflow 		Same as BNO
9 1 0 0 1 Branch if negative and
no overflow
A 1 0 1 0 Branch if no overflow
and no carry
B 1 0 1 1 Branch if no overflow,
no carry & negative
C 1 1 0 0 Branch if no overflow
and not zero
D 1 1 0 1 Same as t=9 
E 1 1 1 0 Branch if no overflow,
no carry & not zero
F 1 1 1 1 Same as t=B 
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