Difference between revisions of "Opcode"

From veswiki
Jump to: navigation, search
Line 64: Line 64:
 
|}
 
|}
  
−
{| border="1" cellspacing="1" cellpadding="4" style="width: 100%"
+
{| class="wikitable sortable" border="1" cellspacing="1" cellpadding="4" style="width: 100%"
 
|+ Table copied from [http://channelf.se/files/channelf/f8_info_%2716_bit_%B5P_architecture%27%2C_Terry_Polhoff_%281979%29.pdf F8_info]<br />Extra data added from [http://www.nyx.net/~lturner/public_html/F8_ins.html L. Turner F8 ins]
 
|+ Table copied from [http://channelf.se/files/channelf/f8_info_%2716_bit_%B5P_architecture%27%2C_Terry_Polhoff_%281979%29.pdf F8_info]<br />Extra data added from [http://www.nyx.net/~lturner/public_html/F8_ins.html L. Turner F8 ins]
 
! rowspan="2" | Mnemonic
 
! rowspan="2" | Mnemonic
Line 71: Line 71:
 
! rowspan="2" | Description
 
! rowspan="2" | Description
 
! colspan="2" | Opcode
 
! colspan="2" | Opcode
−
! colspan="4" | Status Flags
+
! colspan="4" class="unsortable" | Status Flags
 
|-
 
|-
 
! Binary
 
! Binary
Line 79: Line 79:
 
! style="width: 1.5em; cursor: help" title="Carry" | C
 
! style="width: 1.5em; cursor: help" title="Carry" | C
 
! style="width: 1.5em; cursor: help" title="Signed" | S
 
! style="width: 1.5em; cursor: help" title="Signed" | S
−
|-
 
−
! colspan="12" |
 
−
===8-bit Transfers===
 
 
|-  
 
|-  
 
| LR A, r || 1 || 1 || A = r || %0100xxxx || $4x || - || - || - || -
 
| LR A, r || 1 || 1 || A = r || %0100xxxx || $4x || - || - || - || -
Line 124: Line 121:
 
|-  
 
|-  
 
| CLR || 1 || 1 || A = 0 || %01110000 || $70 ||- ||- ||- ||-
 
| CLR || 1 || 1 || A = 0 || %01110000 || $70 ||- ||- ||- ||-
−
|-
 
−
! colspan="12" |
 
−
 
−
|-
 
−
! rowspan="2" | Mnemonic
 
−
! rowspan="2" | Length
 
−
! rowspan="2" | Cycles
 
−
! rowspan="2" | Description
 
−
! colspan="2" | Opcode
 
−
! colspan="4" | Status Flags
 
−
|-
 
−
! Binary
 
−
! Hex
 
−
! style="width: 1.5em; cursor: help" title="Overflow" | O
 
−
! style="width: 1.5em; cursor: help" title="Zero" | Z
 
−
! style="width: 1.5em; cursor: help" title="Carry" | C
 
−
! style="width: 1.5em; cursor: help" title="Signed" | S
 
−
|-
 
−
! colspan="12" |
 
−
 
−
===16-bit Transfers===
 
 
|-  
 
|-  
 
| LR K, P || 1 || 4 || R12=P(upper), R13=P(lower) || %00001000 || $08 ||- ||- ||- ||-
 
| LR K, P || 1 || 4 || R12=P(upper), R13=P(lower) || %00001000 || $08 ||- ||- ||- ||-
Line 163: Line 139:
 
|-  
 
|-  
 
| ADC || 1 || 2.5 || DC0=DC0+A || %10001110 || $8E ||- ||- ||- ||-
 
| ADC || 1 || 2.5 || DC0=DC0+A || %10001110 || $8E ||- ||- ||- ||-
−
|-
 
−
! colspan="12" |
 
−
 
−
===8-bit Arithmetic===
 
 
|-  
 
|-  
 
| AS r || 1 || 1 || A = A + r || %1100xxxx || $Cx || X || X || X || X
 
| AS r || 1 || 1 || A = A + r || %1100xxxx || $Cx || X || X || X || X
Line 172: Line 144:
 
| AI n || 2 || 2.5 || A = A + n || %00100100 %xxxxxxxx || $24 $xx || X || X || X || X
 
| AI n || 2 || 2.5 || A = A + n || %00100100 %xxxxxxxx || $24 $xx || X || X || X || X
 
|-
 
|-
−
! colspan="12" |
 
−
 
−
===Jumps===
 
−
|-
 
 
| BR n || 2 || 3.5 || P0 = P0 + 1 + n || %10010000 %xxxxxxxx || $90 $xx ||- ||- ||- ||-  
 
| BR n || 2 || 3.5 || P0 = P0 + 1 + n || %10010000 %xxxxxxxx || $90 $xx ||- ||- ||- ||-  
 
|-  
 
|-  
Line 201: Line 169:
 
|-  
 
|-  
 
| LR P0, Q || 1 || 4 || P0(upper) = R14, P0(lower) = R15 || %00001101 || $0D ||- ||- ||- ||-
 
| LR P0, Q || 1 || 4 || P0(upper) = R14, P0(lower) = R15 || %00001101 || $0D ||- ||- ||- ||-
−
|-
 
−
! colspan="12" |
 
−
 
−
|-
 
−
! rowspan="2" | Mnemonic
 
−
! rowspan="2" | Length
 
−
! rowspan="2" | Cycles
 
−
! rowspan="2" | Description
 
−
! colspan="2" | Opcode
 
−
! colspan="4" | Status Flags
 
−
|-
 
−
! Binary
 
−
! Hex
 
−
! style="width: 1.5em; cursor: help" title="Overflow" | O
 
−
! style="width: 1.5em; cursor: help" title="Zero" | Z
 
−
! style="width: 1.5em; cursor: help" title="Carry" | C
 
−
! style="width: 1.5em; cursor: help" title="Signed" | S
 
−
|-
 
−
! colspan="12" |
 
−
 
−
===Call/Return===
 
−
|-
 
−
! colspan="12" |
 
−
===Shifts===
 
 
|-  
 
|-  
 
| SL 1 || 1 || 1 || Shift A left one bit, fill with %0 || %00010011 || $13 || 0 || X || 0 || X
 
| SL 1 || 1 || 1 || Shift A left one bit, fill with %0 || %00010011 || $13 || 0 || X || 0 || X
Line 234: Line 178:
 
| SR 4 || 1 || 1 || Shift A right four bits, fill with %0000 || %00010100 || $14 || 0 || X || 0 || 1
 
| SR 4 || 1 || 1 || Shift A right four bits, fill with %0000 || %00010100 || $14 || 0 || X || 0 || 1
 
|-
 
|-
−
! colspan="12" |
 
−
 
−
===Misc.===
 
−
|-
 
 
| COM || 1 || 1 || A = [[complement] of A (inverse) || %00011000 || $18 || 0 || X || 0 || X
 
| COM || 1 || 1 || A = [[complement] of A (inverse) || %00011000 || $18 || 0 || X || 0 || X
 
|-  
 
|-  
−
| NOP || 1 || 1 || No operation (cycle waster) || %00101011 || $2B || || || ||
+
| NOP || 1 || 1 || No operation (cycle waster) || %00101011 || $2B ||- ||- ||- ||-  
−
|-  
 
−
| EI || 1 || 1 || Enable interrupts in status register bit 4 || %00011011 || $1B || || || ||
 
 
|-  
 
|-  
−
| DI || 1 || 1 || Disable interrupts in status register bit 4 || %00011010 || $1A || || || ||  
+
| EI || 1 || 1 || Enable interrupts in status register bit 4 || %00011011 || $1B ||- ||- ||- ||-
 
|-  
 
|-  
−
! colspan="12" |
+
| DI || 1 || 1 || Disable interrupts in status register bit 4 || %00011010 || $1A ||- ||- ||- ||-
−
 
 
−
===Input/Output===
 
 
|-  
 
|-  
 
| IN n || 2 || 4 || Input port n to A|| %00100110 %xxxxxxxx || $26 $xx ||0 ||X ||0 ||X
 
| IN n || 2 || 4 || Input port n to A|| %00100110 %xxxxxxxx || $26 $xx ||0 ||X ||0 ||X
Line 257: Line 193:
 
|-  
 
|-  
 
| OUTS i || 1 || 2 (i=0-1)<br />4 (i=4-7) || Output A to port i || %1011xxxx || $Bx ||- ||- ||- ||-
 
| OUTS i || 1 || 2 (i=0-1)<br />4 (i=4-7) || Output A to port i || %1011xxxx || $Bx ||- ||- ||- ||-
 +
|-
 +
| LNK || 1 || 1 || A <- (A)+(C) || %00011001 || $19 ||X ||X ||X ||X
 +
|-
 +
| POP || 1 || 2 || PC0 <- PC1, A destroyed || %00011100 || $1C ||- ||- ||- ||-
 +
| INC || 1 || 1 || A <- (A)+1 || %00011111 || $1F ||X ||X ||X ||X
 
|}
 
|}
−
 
−
''(rest of table to follow)''
 

Revision as of 14:58, 20 November 2012

An opcode is a number representing an instruction for the F8 processor system to follow for example $2B means No Operation (NOP). Programs are made up of opcodes, which instruct the F8 System to do something, such as load a register with a value, perform arithmetic on a register, change the program counter (jump), or input or output data through the ports. Opcodes in the F8 System are each one byte wide, though some may be followed by an address (two bytes) or a value for the opcode to use. Often people refer to the mnemonics as opcodes but these are just constructed so we people can understand it easier than just looking at rows of numbers. NOP is such a mnemonic and can be used in an assembly program listing.

The Instruction Set

In the information for each opcode, the following notations are used:

Opcode Notations
A Accumulator
Ri Scratchpad register i (r0-r11)
P0 Program counter
P Program counter Stack
DC0 Data counter
DC1 Alternate data counter
W Status register
ISAR Indirect Scratchpad Address Register
r Scratchpad addressing as:
0 to 11 Select registers r0-r11
I Select ISAR, then ISAR = ISAR + 1
S Select ISAR
D Select ISAR, then ISAR = ISAR - 1
t 3-bit constant
i 4-bit constant
n 8-bit constant
nn 16-bit constant
( ) Contents of memory (e.g., (DC))
x Binary value placeholder
Status Flag Notations
O Overflow Flag
Z Zero Flag
C Carry Flag
S Sign Flag
0 Resets status flag
1 Sets status flag
X Modifies status flag
Table copied from F8_info
Extra data added from L. Turner F8 ins
Mnemonic Length Cycles Description Opcode Status Flags
Binary Hex O Z C S
LR A, r 1 1 A = r  %0100xxxx $4x - - - -
LR A, Ku 1 1 A = R12  %00000000 $00 - - - -
LR A, Kl 1 1 A = R13  %00000001 $01 - - - -
LR A, Qu 1 1 A = R14  %00000010 $02 - - - -
LR A, Ql 1 1 A = R15  %00000011 $03 - - - -
LR r, A 1 1 r = A  %0101xxxx $5x - - - -
LR Ku, A 1 1 R12 = A  %00000100 $04 - - - -
LR Kl, A 1 1 R13 = A  %00000101 $05 - - - -
LR Qu, A 1 1 R14 = A  %00000110 $06 - - - -
LR Ql, A 1 1 R15 = A  %00000111 $07 - - - -
LM 1 2.5 A = (DC0), DC0 = DC0 + 1  %00010110 $16 - - - -
ST 1 2.5 (DC0) = A, DC0 = DC0 + 1  %00010111 $17 - - - -
LR A, IS 1 1 A = ISAR  %00001010 $0A - - - -
LR IS, A 1 1 ISAR = A  %00001011 $0B - - - -
LR J, W 1 1 R9 = W  %00011101 $1D - - - -
LR W, J 1 2 W = R9  %00011110 $1E - - - -
LISU i 1 1 ISAR(upper) = i  %01100xxx $6x - - - -
LISL i 1 1 ISAR(lower) = i  %01101xxx $6x - - - -
LI n 2 2.5 A = n  %00100000 %xxxxxxxx $20 $xx - - - -
LIS i 1 1 A = i  %0111xxxx $7x - - - -
CLR 1 1 A = 0  %01110000 $70 - - - -
LR K, P 1 4 R12=P(upper), R13=P(lower)  %00001000 $08 - - - -
LR H, DC 1 4 R10=DC0(upper), R11=DC0(lower)  %00010001 $11 - - - -
LR Q, DC 1 4 R14=DC0(upper), R15=DC0(lower)  %00001110 $0E - - - -
LR P, K 1 4 P(upper)=R12, P(lower)=R13  %00001001 $09 - - - -
LR DC, H 1 4 DC0(upper)=R10, DC0(lower)=R11  %00010000 $10 - - - -
LR DC, Q 1 4 DC0(upper)=R14, DC0(lower)=R15  %00001111 $0F - - - -
DCI nn 3 6 DC0=nn  %00101010 %xxxxxxxx %xxxxxxxx $2A $xx $xx - - - -
XDC 1 2 DC0=DC1, DC1=DC0  %00101100 $2C - - - -
ADC 1 2.5 DC0=DC0+A  %10001110 $8E - - - -
AS r 1 1 A = A + r  %1100xxxx $Cx X X X X
AI n 2 2.5 A = A + n  %00100100 %xxxxxxxx $24 $xx X X X X
BR n 2 3.5 P0 = P0 + 1 + n  %10010000 %xxxxxxxx $90 $xx - - - -
BC n 2 3 (no branch)
3.5 (branch) 		if CARRY: P0 = P0 + 1 + n  %10000010 %xxxxxxxx $82 $xx - - - -
BNC n 2 3 (no branch)
3.5 (branch) 		if NO CARRY: P0 = P0 + 1 + n  %10010010 %xxxxxxxx $92 $xx - - - -
BP n 2 3 (no branch)
3.5 (branch) 		if POSITIVE: P0 = P0 + 1 + n  %10000001 %xxxxxxxx $81 $xx - - - -
BM n 2 3 (no branch)
3.5 (branch) 		if NEGATIVE: P0 = P0 + 1 + n  %10010001 %xxxxxxxx $91 $xx - - - -
BZ n 2 3 (no branch)
3.5 (branch) 		if ZERO: P0 = P0 + 1 + n  %10000100 %xxxxxxxx $84 $xx - - - -
BNZ n 2 3 (no branch)
3.5 (branch) 		if NOT ZERO: P0 = P0 + 1 + n  %10010100 %xxxxxxxx $94 $xx - - - -
BNO n 2 3 (no branch)
3.5 (branch) 		if NO OVERFLOW: P0 = P0 + 1 + n  %10011000 %xxxxxxxx $98 $xx - - - -
BT t, n 2 3 (no branch)
3.5 (branch) 		AND bitmask t with W, if result = TRUE: P0 = P0 + 1 + n  %10000xxx %xxxxxxxx $8x - - - -
BF i, n 2 3 (no branch)
3.5 (branch) 		AND bitmask i with W, if result = FALSE: P0 = P0 + 1 + n  %1001xxxx %xxxxxxxx $9x - - - -
BR7 n 2 2 (no branch)
2.5 (branch) 		if ISAR(lower) != 7: P0 = P0 + 1 + n  %10001111 %xxxxxxxx $8F $xx - - - -
JMP nn 3 5.5 P0 = nn, A is destroyed  %00101001 %xxxxxxxx %xxxxxxxx $29 $xx $xx - - - -
LR P0, Q 1 4 P0(upper) = R14, P0(lower) = R15  %00001101 $0D - - - -
SL 1 1 1 Shift A left one bit, fill with %0  %00010011 $13 0 X 0 X
SL 4 1 1 Shift A left four bits, fill with %0000  %00010101 $15 0 X 0 X
SR 1 1 1 Shift A right one bit, fill with %0  %00010010 $12 0 X 0 1
SR 4 1 1 Shift A right four bits, fill with %0000  %00010100 $14 0 X 0 1
COM 1 1 A = [[complement] of A (inverse)  %00011000 $18 0 X 0 X
NOP 1 1 No operation (cycle waster)  %00101011 $2B - - - -
EI 1 1 Enable interrupts in status register bit 4  %00011011 $1B - - - -
DI 1 1 Disable interrupts in status register bit 4  %00011010 $1A - - - -
IN n 2 4 Input port n to A  %00100110 %xxxxxxxx $26 $xx 0 X 0 X
INS i 1 2 (i=0-1)
4 (i=4-7) 		Input port i to A  %1010xxxx $Ax 0 X 0 X
OUT n 2 4 Output A to port n  %00100111 %xxxxxxxx $27 $xx - - - -
OUTS i 1 2 (i=0-1)
4 (i=4-7) 		Output A to port i  %1011xxxx $Bx - - - -
LNK 1 1 A <- (A)+(C)  %00011001 $19 X X X X
POP 1 2 PC0 <- PC1, A destroyed  %00011100 $1C - - - - INC 1 1 A <- (A)+1  %00011111 $1F X X X X
Retrieved from "http://channelf.se/veswiki/index.php?title=Opcode&oldid=269"