Difference between revisions of "ROMC"
(Created page with "To save on capsule pins the different parts in the F8 processor system communicates with the ROMC-bus.<br> Instead of an address bus each device has its own Program Counter (P...") |
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| Line 154: | Line 154: | ||
|1B | |1B | ||
|L | |L | ||
| − | | | + | |During the prior cycle, the data bus specified the address of an I/O port. The device containing the <br> |
| + | addressed I/O port must place the contents of the I/O port on the data bus. (Note that the contents of <br> | ||
| + | timer and interrupt control registers cannot be read back onto the data bus.) | ||
|- | |- | ||
|11100 | |11100 | ||
|1C | |1C | ||
|L or S | |L or S | ||
| − | | | + | |None. |
|- | |- | ||
|11101 | |11101 | ||
Revision as of 10:22, 8 September 2016
To save on capsule pins the different parts in the F8 processor system communicates with the ROMC-bus.
Instead of an address bus each device has its own Program Counter (PC).
The different states
| ROMC Signal functions | |||
|---|---|---|---|
| ROMC 43210 |
HEX |
Cycle length |
Function |
| 00000 | 00 | S,L | Instruction Fetch. The device whose address space includes the contents of the PCO register must place on the data bus the op code addressed by PC0; then all devices increment the contents of PC0. |
| 00001 | 01 | L | The device whose address space includes the contents of the PCO register must place on the data bus the contents of the memory location addressed by PC0; then all devices add the 8-bit value on the data |
| 00010 | 02 | L | The device whose DC0 addresses a memory word within the address space of that device must place on the data bus the contents of the memory location addressed by DC0; then all devices |
| 00011 | 03 | L,S | |
| 00100 | 04 | S | |
| 00101 | 05 | L | |
| 00110 | 06 | L | |
| 00111 | 07 | L | |
| 01000 | 08 | L | |
| 01001 | 09 | L | |
| 01010 | 0A | L | |
| 01011 | 0B | L | |
| 01100 | 0C | L | |
| 01101 | 0D | S | |
| 01110 | 0E | L | |
| 01111 | 0F | L | |
| 10000 | 10 | L | |
| 10001 | 11 | L | |
| 10010 | 12 | L | |
| 10011 | 13 | L | |
| 10100 | 14 | L | |
| 10101 | 15 | L | |
| 10110 | 16 | L | |
| 10111 | 17 | L | |
| 11000 | 18 | L | |
| 11001 | 19 | L | |
| 11010 | 1A | L | |
| 11011 | 1B | L | During the prior cycle, the data bus specified the address of an I/O port. The device containing the addressed I/O port must place the contents of the I/O port on the data bus. (Note that the contents of |
| 11100 | 1C | L or S | None. |
| 11101 | 1D | S | Devices with DC0 and DC1 registers must switch registers. Devices without a DC1 register perform no operation. |
| 11110 | 1E | L | The device whose address space includes the contents of PCO must place the low order byte of PCO onto the data bus. |
| 11111 | 1F | L | The device whose address space includes the contents of PCO must place the high order byte of PCO onto the data bus. |
