Difference between revisions of "ROMC"
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Instead of an address bus each device has its own Program Counter (PC). <br> | Instead of an address bus each device has its own Program Counter (PC). <br> | ||
| − | A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles). | + | A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles). <br> |
The different states | The different states | ||
Revision as of 16:03, 26 September 2022
To save on capsule pins the different parts in the F8 processor system communicates with the ROMC-bus.
Instead of an address bus each device has its own Program Counter (PC).
A Short cycle is 4 clock periods long, a Long cycle is 6 clock periods long (sometimes referred to 1.5 cycles).
The different states
| ROMC Signal functions | |||
|---|---|---|---|
| ROMC 43210 |
HEX |
Cycle length |
Function |
| 00000 | 00 | S,L | Instruction Fetch. The device whose address space includes the contents of the PC0 register must place on the data bus the op code addressed by PC0; then all devices increment the contents of PC0. |
| 00001 | 01 | L | The device whose address space includes the contents of the PC0 register must place on the data bus the contents of the memory location addressed by PC0; then all devices add the 8-bit value on the data |
| 00010 | 02 | L | The device whose DC0 addresses a memory word within the address space of that device must place on the data bus the contents of the memory location addressed by DC0; then all devices |
| 00011 | 03 | L,S | Similar to 00, except that it is used for Immediate Operand fetches (using PC0) instead of instruction fetches. |
| 00100 | 04 | S | Copy the contents of PC1 into PC0. |
| 00101 | 05 | L | Store the data bus contents into the memory location pointed to by DC0; increment DC0. |
| 00110 | 06 | L | Place the high order byte of DC0 on the data bus. |
| 00111 | 07 | L | Place the high order byte of PC1 on the data bus. |
| 01000 | 08 | L | All devices copy the contents of PC0 into PC1. The CPU outputs zero on the data bus in this ROMC state. Load the data bus into both halves of PC0, thus clearing the register. |
| 01001 | 09 | L | The device whose address space includes the contents of the DC0 register must place the low order byte of DC0 onto the data bus. |
| 01010 | 0A | L | All devices add the 8-bit value on the data bus, treated as a signed binary number, to the data counter. |
| 01011 | 0B | L | The device whose address space includes the value in PC1 must place the low order byte of PC1 on the data bus. |
| 01100 | 0C | L | The device whose address space includes the contents of the PC0 register must place the contents of the memory word addressed by PC0 onto the data bus; then all devices move the value that has just |
| 01101 | 0D | S | All devices store in PC1 the current contents of PC0, incremented by 1; PC0 is unaltered. |
| 01110 | 0E | L | The device whose address space includes the contents of PC0 must place the contents of the word adressed by PC0 onto the data bus. The value on the data bus is then moved tot the low order byte |
| 01111 | 0F | L | The interrupting device with highest priority must place the low order byte of the interrupt vector on the data bus. All devices must copy the contents of PC0 into PC1. All devices must move the contents of |
| 10000 | 10 | L | Inhibit any modification to the interrupt priority logic. |
| 10001 | 11 | L | The device whose memory space includes the contents of PC0 must place the contents of the addressed memory word onto the data bus. All devices must then move the contents of the data bus |
| 10010 | 12 | L | All devices copy the contents of PC0 into PC1. All devices then move the contents of the data bus into the low order byte of PC0. |
| 10011 | 13 | L | The interrupting device with highest priority must move the high order half of the interrupt vector onto data bus. All devices must move the contents of the data bus into the high order byte of PC0. The |
| 10100 | 14 | L | All devices move the contents of the data bus into the high low order byte of PC0. |
| 10101 | 15 | L | All devices move the contents of the data bus into the high order byte of PC1. |
| 10110 | 16 | L | All devices move the contents of the data bus into the high order byte of DC0. |
| 10111 | 17 | L | All devices move the contents of the data bus into the low order byte of PC0. |
| 11000 | 18 | L | All devices move the contents of the data bus into the low order byte of PC1. |
| 11001 | 19 | L | All devices move the contents of the data bus into the low order byte of DC0. |
| 11010 | 1A | L | During the prior cycle, an I/O port timer or interrupt control register was addressed; the device containing the addressed port must move the current contents of the data bus into the addressed port. |
| 11011 | 1B | L | During the prior cycle, the data bus specified the address of an I/O port. The device containing the addressed I/O port must place the contents of the I/O port on the data bus. (Note that the contents of |
| 11100 | 1C | L or S | None. |
| 11101 | 1D | S | Devices with DC0 and DC1 registers must switch registers. Devices without a DC1 register perform no operation. |
| 11110 | 1E | L | The device whose address space includes the contents of PC0 must place the low order byte of PC0 onto the data bus. |
| 11111 | 1F | L | The device whose address space includes the contents of PC0 must place the high order byte of PC0 onto the data bus. |
