Opcode
The CPU of a digital computer responds to a series of ones and zeros read from memory. The pattern of these, that determine what the CPU is supposed to do, are called Operation Codes or opcode. As an example the opcode $2B on the F8 System means No Operation (NOP). Programs are made up of opcodes which instruct the F8 System to do something, such as load a register with a value, perform arithmetic on a register, change the program counter (jump) or input or output data through the ports.
Opcodes in the F8 System are each one byte wide, though some may be followed by an address (two bytes) or a value for the opcode to use, these extra bytes are called operands and an opcode with its operand is called an instruction and the complete set for a CPU is called an Instruction Set.
Instead of programming these numbers directly (Machine Code Programming) programmers came up with the mnemonic names and wrote programs to translate such code into machine code. This mnemonic form of programming is called Assembly Language. Below is a table showing both types, if you choose Assembly Language then DASM or f8tool are free Assemblers for the F8 System.
The Instruction Set
In the information for each opcode, the following notations are used:
Opcode Notations  

A  Accumulator  
Ri  First registers i (r0r11 [HU,HL=r10,11], KU, KL, QU, QL)  
P0  Program counter  
P  Program counter Stack (PC1)  
DC0  Data counter  
DC1  Data counter storage  
W  Status register, exhange only via the J register (R9)  
ISAR  Indirect Scratchpad Address Register  
r  Scratchpad addressing as:
 
t  3bit constant  
i  4bit constant  
n  8bit constant  
mn  16bit constant  
( )  Contents of register (e.g.(R11) or (DC))  
x  Binary value placeholder  
Status Flag Notations  
O  Overflow Flag  
Z  Zero Flag  
C  Carry Flag  
S  Sign Flag  
0  Resets status flag  
1  Sets status flag  
X  Modifies status flag 
Mnemonic  Length  Cycles  Description  Opcode  Status Flags  

Binary  Hex  O  Z  C  S  
LR A, KU  1  1  A ← (KU)  %00000000  $00         
LR A, KL  1  1  A ← (KL)  %00000001  $01         
LR A, QU  1  1  A ← (QU)  %00000010  $02         
LR A, QL  1  1  A ← (QL)  %00000011  $03         
LR KU, A  1  1  KU ← (A)  %00000100  $04         
LR KL, A  1  1  KL ← (A)  %00000101  $05         
LR QU, A  1  1  QU ← (A)  %00000110  $06         
LR QL, A  1  1  QL ← (A)  %00000111  $07         
LR K, P  1  4  KU ← (PC1U), KL ← (PC1L)  %00001000  $08         
LR P, K  1  4  PC1U ← (KU), PC1L ← (KL)  %00001001  $09         
LR A, IS  1  1  A ← (ISAR)  %00001010  $0A         
LR IS, A  1  1  ISAR ← (A)  %00001011  $0B         
PK  1  2.5  PC1 ← (PC0), PC0L ← (KL), PC0U ← (KU)  %00001100  $0C         
LR P0, Q  1  4  PC0L ← (QL), PC0U ← (QU)  %00001101  $0D         
LR Q, DC  1  4  QU ← (DC0U), QL ← (DC0L)  %00001110  $0E         
LR DC, Q  1  4  DC0U ← (QU), DC0L ← (QL)  %00001111  $0F         
LR DC, H  1  4  DC0U ← (R10), DC0L ← (R11)  %00010000  $10         
LR H, DC  1  4  R10 ← (DC0U), R11 ← (DC0L)  %00010001  $11         
SR 1  1  1  Shift (A) right one bit, fill with %0  %00010010  $12  0  X  0  1 
SL 1  1  1  Shift (A) left one bit, fill with %0  %00010011  $13  0  X  0  X 
SR 4  1  1  Shift (A) right four bits, fill with %0000  %00010100  $14  0  X  0  1 
SL 4  1  1  Shift (A) left four bits, fill with %0000  %00010101  $15  0  X  0  X 
LM  1  2.5  A ← ((DC0)), DC0 ← DC0 + 1  %00010110  $16         
ST  1  2.5  DC0 ← (A), DC0 ← DC0 + 1  %00010111  $17         
COM  1  1  A ← (A)⊕$FF [invert/complement]  %00011000  $18  0  X  0  X 
LNK  1  1  A ← (A)+(C) (add carry from previous operation)  %00011001  $19  X  X  X  X 
DI  1  1  Disable interrupts, status register bit 4  %00011010  $1A         
EI  1  1  Enable interrupts, status register bit 4  %00011011  $1B         
POP  1  2  PC0 ← (PC1)  %00011100  $1C         
LR W, J  1  1  W ← (R9)  %00011101  $1D         
LR J, W  1  2  R9 ← (W)  %00011110  $1E         
INC  1  1  A ← (A)+1  %00011111  $1F  X  X  X  X 
LI n  2  2.5  A ← n  %00100000 %xxxxxxxx  $20 $xx         
NI n  2  2.5  A ← (A) AND n  %00100001 %xxxxxxxx  $21 $xx  0  X  0  X 
OI n  2  2.5  A ← (A) OR n  %00100010 %xxxxxxxx  $22 $xx  0  X  0  X 
XI n  2  2.5  A ← (A)⊕n  %00100011 %xxxxxxxx  $23 $xx  0  X  0  X 
AI n  2  2.5  A ← (A)+n  %00100100 %xxxxxxxx  $24 $xx  X  X  X  X 
CI n  2  2.5  n+!(A)+1 (nA), Only set status  %00100101 %xxxxxxxx  $25 $xx  X  X  X  X 
IN n  2  4  Data Bus ← Port n, A ← (Port n)  %00100110 %xxxxxxxx  $26 $xx  0  X  0  X 
OUT n  2  4  Data Bus ← Port n, Port n ← (A)  %00100111 %xxxxxxxx  $27 $xx         
PI mn  3  6.5  A ← m, PC1 ← (PC0)+1, PC0L ← n, PC0U ← (A)  %00101000 %xxxxxxxx %xxxxxxxx  $28 $xx $xx         
JMP mn  3  5.5  A ← m, PC0L ← n, PC0U ← (A) [A is destroyed]  %00101001 %xxxxxxxx %xxxxxxxx  $29 $xx $xx         
DCI mn  3  6  DC0U ← m, PC0+1, DC0L ← n, PC0+1  %00101010 %xxxxxxxx %xxxxxxxx  $2A $xx $xx         
NOP  1  1  No operation (cycle waster)  %00101011  $2B         
XDC  1  2  DC0,DC1 ← DC1,DC0  %00101100  $2C         
DS r  1  1.5  r ← (r)+$FF, [decrease scratchpad byte]  %0011xxxx  $3x  X  X  X  X 
LR A, r  1  1  A ← (r)  %0100xxxx  $4x         
LR A, HU  1  1  A ← (HU)  %01001010  $4A         
LR A, HL  1  1  A ← (HL)  %01001011  $4B         
LR r, A  1  1  r ← (A)  %0101xxxx  $5x         
LR HU, A  1  1  HU ← (A)  %01011010  $5A         
LR HL, A  1  1  HL ← (A)  %01011011  $5B         
LISU i  1  1  ISARU ← i  %01100xxx  $6x         
LISL i  1  1  ISARL ← i  %01101xxx  $6x         
CLR  1  1  A←0  %01110000  $70         
LIS i  1  1  A ← i  %0111xxxx  $7x         
BT t, n  2  3 (no branch) 3.5 (branch) 
AND bitmask t with W, if result is not 0: PC0←PC0+n+1 See table below 
%10000xxx %xxxxxxxx  $8x         
BP n  2  3 (no branch) 3.5 (branch) 
if POSITIVE (sign bit 0) : PC0←PC0+n+1  %10000001 %xxxxxxxx  $81 $xx         
BC n  2  3 (no branch) 3.5 (branch) 
if CARRY: PC0←PC0+n+1  %10000010 %xxxxxxxx  $82 $xx         
BZ n  2  3 (no branch) 3.5 (branch) 
if ZERO: PC0←PC0+n+1  %10000100 %xxxxxxxx  $84 $xx         
AM  1  2.5  A ← (A)+((DC0)), DC0+1  %10001000  $88  X  X  X  X 
AMD  1  2.5  A ← (A)+((DC0)) decimal adjusted, DC0+1  %10001001  $89  X  X  X  X 
NM  1  2.5  A ← (A)AND((DC0)),DC0+1  %10001010  $8A  0  X  0  X 
OM  1  2.5  A ← (A)OR((DC0)),DC0+1  %10001011  $8B  0  X  0  X 
XM  1  2.5  A ← (A)⊕((DC0)),DC0+1  %10001100  $8C  0  X  0  X 
CM  1  2.5  ((DC0))A only set status, DC0+1  %10001101  $8D  X  X  X  X 
ADC  1  2.5  DC0 ← (DC0)+(A)  %10001110  $8E         
BR7 n  2  2 (no branch) 2.5 (branch) 
if ISARL != 7: PC0 ← (PC0) + n +1  %10001111 %xxxxxxxx  $8F $xx         
BR n  2  3.5  PC0 ← (PC0)+n+1  %10010000 %xxxxxxxx  $90 $xx         
BF i, n  2  3 (no branch) 3.5 (branch) 
AND bitmask i with W, if result = FALSE: PC0 ← (PC0)+n+1 See table below 
%1001xxxx %xxxxxxxx  $9x         
BM n  2  3 (no branch) 3.5 (branch) 
if NEGATIVE: PC0 ← (PC0)+n+1  %10010001 %xxxxxxxx  $91 $xx         
BNC n  2  3 (no branch) 3.5 (branch) 
if NO CARRY: PC0 ← (PC0)+n+1  %10010010 %xxxxxxxx  $92 $xx         
BNZ n  2  3 (no branch) 3.5 (branch) 
if NOT ZERO: PC0 ← (PC0)+n+1  %10010100 %xxxxxxxx  $94 $xx         
BNO n  2  3 (no branch) 3.5 (branch) 
if NO OVERFLOW: PC0 ← (PC0)+n+1  %10011000 %xxxxxxxx  $98 $xx         
INS i  1  2 (i=01) 4 (i=215) 
A ← (Port i), if i=215: Data Bus ← Port Address, A ← (Port i)  %1010xxxx  $Ax  0  X  0  X 
OUTS i  1  2 (i=01) 4 (i=215) 
Port i ← (A), if i=215: Data Bus ← Port Address, Port i ← (A)  %1011xxxx  $Bx         
AS r  1  1  A ← (A)+(r)  %1100xxxx  $Cx  X  X  X  X 
ASD r  1  2  A ← (A)+(r) (decimal)  %1101xxxx  $Dx  X  X  X  X 
XS r  1  1  A ← (A)⊕(r)  %1110xxxx  $Ex  0  X  0  X 
NS r  1  1  A ← (A)AND(r)  %1111xxxx  $Fx  0  X  0  X 
IRQ  5.5  PC0L ← Int address(l), PC0U ← Int.Address(u), PC1<PC0          
RESET  3.5  PC0 ← 0, PC1 ← PC0         
The BT instruction
Branch conditions for BT instruction  

Operand t 
Status flags tested  Definition 
Comments  
zero  carry  sign  
0  0  0  0  Do not branch  An effective 3 cycle NOOP 
1  0  0  1  Branch if Positive  Same as BP 
2  0  1  0  Branch on Carry  Same as BC 
3  0  1  1  Branch if Positive or on Carry 

4  1  0  0  Branch if Zero  Same as BZ 
5  1  0  1  Branch if Positive  Same as t=1 
6  1  1  0  Branch if Zero or on Carry 

7  1  1  1  Branch if Positive or on Carry 
Same as t=3 
The BF instruction
Branch conditions for BF instruction  

Operand t 
Status flags tested  Definition 
Comments  
ovf  zero  carry  sign  
0  0  0  0  0  Unconditional branch relative 

1  0  0  0  1  Branch on negative  Same as BM 
2  0  0  1  0  Branch if no carry  Same as BNC 
3  0  0  1  1  Branch if no carry and negative 

4  0  1  0  0  Branch if not zero  Same as BNZ 
5  0  1  0  1  Same as t=1  
6  0  1  1  0  Branch if no carry and result is zero 

7  0  1  1  1  Same as t=3  
8  1  0  0  0  Branch if there is no overflow 
Same as BNO 
9  1  0  0  1  Branch if negative and no overflow 

A  1  0  1  0  Branch if no overflow and no carry 

B  1  0  1  1  Branch if no overflow, no carry & negative 

C  1  1  0  0  Branch if no overflow and not zero 

D  1  1  0  1  Same as t=9  
E  1  1  1  0  Branch if no overflow, no carry & not zero 

F  1  1  1  1  Same as t=B 