Status register

From veswiki
Jump to: navigation, search

The status register is an 8-bit register used by the F8 to store the results of a previous operation, or as a flag to allow interrupts. Only the lower 5 bits of the register are used. In the LR opcode, the status register can be accessed using the letter W, though it can only be transferred back and forth from the register J, or scratchpad register 9.

The status register is primarily affected by mathematical opcodes, such as addition or any binary logic. When branching, the opcodes apply a bitmask to the status register and determine whether the condition is true or not.

Status Register Bits

This table breaks down the status register bit-by-bit (LSB is bit 0):

Bit Name Description
0 Sign Carries the sign of the last operation (positive, negative)
1 Carry Set if the last operation resulted in a carry.
2 Zero Set if the value of the last operation was 0.
3 Overflow Set if the last operation resulted in too large a number
4 ICB Set if interrupts are to be enabled (use EI, DI)
5 (unused)  
6 (unused)  
7 (unused)